Processing System With Interspersed Processors DMA-FIFO

Patent metadata

Field	Value
Publication number	US-2016335207-A1
Application number	US-201615219018-A
Country	US
Kind code	A1
Filing date	Jul 25, 2016
Priority date	Nov 21, 2012
Publication date	Nov 17, 2016
Grant date	—

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

First claim

What is claimed is:

1 . An apparatus, comprising:
a plurality of processors configured to execute at least one program; a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of the plurality of processors; a plurality of configurable communication elements, wherein each configurable communication element of the plurality of configurable communication elements includes a plurality of communication ports, a first memory, and a routing engine; wherein to execute the at least one program, each processor of the subset of the plurality of processors is configured to communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected memories of the plurality of memories and selected configurable communication elements of the plurality of configurable communication elements.

2 . The apparatus of claim 1 , wherein each DMA engine of a subset of the plurality of DMA engines is configured to operate on a common portion of a particular memory of the plurality of memories to implement a first out (FIFO) buffer.

3 . The apparatus of claim 2 , wherein to implement the FIFO buffer, each DMA engine of the subset of the plurality of DMA engines is further configured to enable a plurality of read operations to be performed on the FIFO buffer for each single write operation to the FIFO buffer.

4 . The apparatus of claim 1 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a plurality of DMA write (DMAW) engines.

5 . A method for operating a multiprocessor system, the method comprising:
executing at least one program on a plurality of processors, each processor comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; wherein executing at least one program comprises:
at least a subset of the plurality of processors, each of which coupled to a respective one of a plurality of memories, communicating with each other through a plurality of configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; and
controlling a plurality of direct memory access (DMA) engines coupled to one or more of the plurality of memories, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected ones of the communication ports and the plurality of memories.

6 . The method of claim 5 , wherein controlling the plurality of DMA engines comprises implementing one or more first in first out (FIFO) buffers in one or more memories of the plurality of memories.

7 . The method of claim 6 , wherein controlling the plurality of DMA engines further comprises enabling a plurality of read operations to occur to a given one of the one or more FIFO buffers for each single write operation to the given one of the one or more FIFO buffers.

8 . The method of claim 6 , wherein controlling the plurality of DMA engines further comprises enabling a plurality of write operations to occur to a given one of the one or more FIFO buffers for each single read operation to the given one of the one or more FIFO buffers.

9 . The method of claim 6 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a plurality of DMA write (DMAW) engines.

10 . The method of claim 6 , wherein the plurality of DMA engines comprises a plurality of DMA read (DMAR) engines, and a plurality of DMA write (DMAW) engines, wherein controlling the plurality of DMA engines further comprises:
controlling a given one of the plurality of DMAR engines and a given one of the plurality of the DMAW engines; setting a wrap bit dependent upon a determination that a write pointer of the given DMAW advances from an end to a start of a given FIFO buffer of the one or more FIFO buffers; re-setting the wrap bit dependent upon a determination that a read pointer of the given DMAR advances from the end to the start of the given FIFO buffer; comparing the read pointer and the write pointer; and stalling the given DMAR engine and the given DMAW engine dependent upon the comparison and the wrap bit.

11 . The method of claim 10 , wherein controlling the plurality of DMA engines further comprises:
comparing a read pointer for each DMAR engine of the plurality of DMAR engines to a write pointer of a respective DMAW engine of the plurality of DMAW engines; stalling each DMAR engine and the respective DMAW engine dependent upon the comparison.

12 . The method of claim 6 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a DMA write (DMAW) engine, and wherein controlling the plurality of DMA engines further comprises:
comparing a read pointer for each DMAR engine of the plurality of DMAR engines to a write pointer of the DMAW engine; stalling the plurality of DMAR engines and the DMAW engine dependent upon the comparison.

13 . The method of claim 8 , wherein the plurality of DMA engines comprises a plurality of DMA write (DMAW) engines, and a DMA read (DMAR) engine, and wherein controlling the plurality of DMA engines further comprises:
comparing a write pointer for each DMAW engine of the plurality of the DMAW engines to a read pointer of the DMAR engine; and stalling the plurality of DMAW engines and the DMAR engine dependent upon the comparison.

14 . The method of claim 5 , wherein controlling the plurality of DMA engines comprises providing a respective plurality of read strides for the plurality of DMA engines.

15 . The method of claim 5 , wherein controlling the plurality of DMA engines comprises providing a respective plurality of write strides for the plurality of DMA engines.

16 . The method of claim 6 , wherein controlling the plurality of DMA engines comprises selecting a subset of the plurality of DMA engines to operate on each of the one or more FIFO buffers.

17 . The method of claim 16 , wherein selecting the subset of the plurality of DMA engines comprises receiving data, wherein selecting the subset of the plurality of DMA engines is dependent upon the received data.

18 . A system, comprising:
a plurality of processors configured to execute at least one program; and a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein each configurable communication element includes:
a plurality of memories, wherein each memory of the plurality of memories is coupled to a respective processor of the plurality of processors; and
a plurality of direct memory access (DMA) engines coupled to one or more of the plurality of memories, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected ones of the communication ports and the plurality of memories;
wherein to execute the at least one program, each processor of a subset of the plurality of processors is configured to:
communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and
control the plurality of direct memory access DMA engines.

19 . The system of claim 15 , wherein to control t

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R
• Bindloss Keith M

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title