Processing system with interspersed processors DMA-FIFO

Patent metadata

Field	Value
Publication number	US-11030023-B2
Application number	US-201615219018-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Nov 21, 2012
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of processors configured to execute at least one program;
a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of the plurality of processors;
a plurality of configurable communication elements, wherein each configurable communication element of the plurality of configurable communication elements includes a plurality of communication ports, a first memory, and a routing engine;
wherein to execute the at least one program, each processor of the subset of the plurality of processors is configured to communicate with at least one other processor of the subset of the plurality of processors via a particular configurable communication element of the plurality of configurable communication element; and
a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is configured to transfer data between selected memories of the plurality of memories and selected configurable communication elements of the plurality of configurable communication elements;
a controller circuit configured to coordinate operation of a first subset of DMA engines of the plurality of DMA engines independent of the plurality of processors; and
wherein the first subset of DMA engines is configured to:
receive respective input data streams and generate a single output data stream with a first data rate by storing the respective input data streams with a second data rate in a buffer located in a portion of a particular memory of the plurality of memories, wherein the first data rate is greater than the second data rate; and
in response to a determination that a particular DMA engine of the plurality of DMA engines cannot receive the single output data stream, signal a second subset of DMA engines sending the respective input data streams to pause before continuing to send the respective input data streams, wherein the particular DMA engine is not included in the first subset of DMA engines.

2. The apparatus of claim 1 , wherein a second subset of the plurality of DMA engines is configured to operate on a common portion of a different memory of the plurality of memories to implement a first in first out (FIFO) buffer.

3. The apparatus of claim 2 , wherein to implement the FIFO buffer, the subset of the plurality of DMA engines is further configured to enable a plurality of read operations to be performed on the FIFO buffer for each single write operation to the FIFO buffer.

4. The apparatus of claim 1 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a plurality of DMA write (DMAW) engines.

5. A method for operating a multiprocessor system, the method comprising:
executing at least one program on a plurality of processors, each processor comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports;
wherein executing the at least one program comprises:
at least a subset of the plurality of processors, each of which coupled to a respective one of a plurality of memories, communicating with each other through a plurality of configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine;
controlling, by a controller circuit independently of the plurality of processors, a plurality of direct memory access (DMA) engines coupled to a particular memory of the plurality of memories, wherein each DMA engine of the plurality of DMA engines is configured to transfer first data between selected ones of the communication ports and the plurality of memories; and
wherein the controlling the plurality of DMA engines includes:
receiving, by the plurality of DMA engines at a first data rate, respective input data streams;
generating, by the plurality of DMA engines, a single output data stream with a second data rate by storing the respective input data streams in a buffer located in a portion of the particular memory, wherein the first data rate is greater than the second data rate;
routing, by a particular DMA engine of the plurality of DMA engines, the single output data stream to a corresponding location; and
in response to determining that the particular DMA engine cannot receive the single output data stream, signal a subset of DMA engines sending the respective input data streams to pause before continuing to send the respective input data streams.

6. The method of claim 5 , wherein controlling the plurality of DMA engines comprises implementing one or more first in first out (FIFO) buffers in one or more memories of the plurality of memories.

7. The method of claim 6 , wherein controlling the plurality of DMA engines further comprises enabling a plurality of read operations to occur to a given one of the one or more FIFO buffers for each single write operation to the given one of the one or more FIFO buffers.

8. The method of claim 6 , wherein controlling the plurality of DMA engines further comprises enabling a plurality of write operations to occur to a given one of the one or more FIFO buffers for each single read operation to the given one of the one or more FIFO buffers.

9. The method of claim 6 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a plurality of DMA write (DMAW) engines.

10. The method of claim 6 , wherein the plurality of DMA engines comprises a plurality of DMA read (DMAR) engines, and a plurality of DMA write (DMAW) engines, wherein controlling the plurality of DMA engines further comprises:
controlling a given one of the plurality of DMAR engines and a given one of the plurality of the DMAW engines;
setting a wrap bit based on a first determination that a write pointer of the given one of the plurality of DMAW engines advances from an end to a start of a given FIFO buffer of the one or more FIFO buffers;
re-setting the wrap bit based on a second determination that a read pointer of the given one of the plurality of DMAR engines advances from the end to the start of the given FIFO buffer;
comparing the read pointer and the write pointer; and
stalling the given DMAR engine and the given one of the plurality DMAW engines dependent upon the wrap bit and a result of comparing the read pointer and the write pointer.

11. The method of claim 10 , wherein controlling the plurality of DMA engines further comprises:
comparing respective read pointers for the plurality of DMAR engines to a corresponding write pointer of a respective DMAW engine of the plurality of DMAW engines; and
stalling the plurality DMAR engines and the respective DMAW engine based on another result of comparing the respective read pointers and the write pointer of the respective DMAW engine.

12. The method of claim 6 , wherein the plurality of DMA engines includes a plurality of DMA read (DMAR) engines and a DMA write (DMAW) engine, and wherein controlling the plurality of DMA engines further comprises:
comparing a read pointer for each DMAR engine of the plurality of DMAR engines to a write pointer of the DMAW engine; and
stalling the plurality of DMAR engines and the DMAW engine based on a result of comparing the read point to the write pointer.

13. The method of claim 8 , wherein the plurality of DMA engines comprises a plurality of DMA write (DMAW) engines, and a DMA read (DMAR) engine, and wherein controlling the plurality of DMA engines further comprises:
comparing a write pointer for each DMAW engine of the plurality of the DMAW engines to a read pointer of the DMAR engine; and
stalling the plurality of DMAW engines and the DMAR engine base

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R
• Bindloss Keith M

Classifications

• G06F15/8038

  Associative processors · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F11/3419

  by assessing time · CPC title