Processor instructions to accelerate FEC encoding and decoding

Patent metadata

Field	Value
Publication number	US-10691451-B2
Application number	US-201615390910-A
Country	US
Kind code	B2
Filing date	Dec 27, 2016
Priority date	Dec 28, 2015
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

First claim

What is claimed is:

1. A processing element, comprising:
a plurality of pipelined operational stages, each operational stage configurable to perform a plurality of data-processing operations;
wherein the processing element is configured to:
at a first time, in response to receiving an M-width approximated min-sum (MAMINSUM) instruction associated with a forward error correction (FEC) encoded signal, wherein the FEC encoded signal comprises a plurality of input values:
configure a first operational stage to determine an absolute value and a sign function of a first input value of the plurality of input values, and determine an absolute value and a sign function of a second input value of the plurality of input values;
configure a second operational stage to determine a minimum of the absolute value of the first input value and the absolute value of the second input value, and determine a final sign function comprising a product of the sign function of the first input value and the sign function of the second input value; and
configure a third operational stage to apply the final sign function to the minimum of the absolute value of the first input value and the absolute value of the second input value; and
iteratively perform the first, second, and third operational stages for the plurality of input values to generate a decoded signal corresponding to the FEC encoded signal; and

at a second time, in response to receiving a different instruction, reconfigure at least one of the first, second, or third operational stages to perform a different function using a different plurality of input values.

2. The processing element of claim 1 , wherein:
the first operational stage is configured to determine the absolute value and the sign function of the first input value, and determine the absolute value and the sign function of the second input value during a first clock cycle;
the second operational stage is configured to determine the minimum of the absolute value of the first input value and the absolute value of the second input value, and determine final sign function during a second clock cycle; and
the third operational stage is configured to apply the final sign function to the minimum of the absolute value of the first input value and the absolute value of the second input value during a third clock cycle.

3. The processing element of claim 2 , wherein the first input value and the second input value constitute a first pair of the plurality of pairs of input values, wherein to iteratively perform the first operational stage,
the first operational stage is configured to determine an absolute value and a sign of each input value of a respective pair of input values during each clock cycle of a plurality of consecutive clock cycles.

4. The processing element of claim 1 , wherein the plurality of pipelined operational stages is considered a first plurality of pipelined operational stages, the processing element further comprising:
a second plurality of pipelined operational stages, wherein the second plurality of pipelined operational stages are configured in the same manner as the first plurality of pipelined operational stages.

5. The processing elements of claim 1 , wherein configuring an operational stage comprises selecting a plurality of data-processing operations to be performed by the operational stage, and selecting registers from which inputs to the selected data-processing operations will be provided.

6. A processing element, comprising:
a dual data-processing pathway configured to:
at a first time, execute a M-width add-sign instruction associated with a forward error correction (FEC) encoded signal, wherein the FEC encoded signal comprises a plurality of input values including a first input operand including a first operand value and a second operand value, and a second input operand including a third operand value and a fourth operand value, wherein, in executing the M-width add-sign instruction, the dual data-processing pathway is configured to:
configure a first operational stage to:
determine a first signed value by applying a first sign function to the first operand value; and
determine a second signed value by applying a second sign function to the second operand value; and

configure a second operational stage to:
add the first signed value to the third operand value; and
add the second signed value to the fourth operand value;

and
at a second time, in response to receiving a second, different instruction, reconfigure the dual data-processing pathway to perform a plurality of data-processing operations other than those configured in response to receiving the M-width add-sign instruction.

7. The processing element of claim 6 , wherein the M-width add-sign instruction further specifies the first sign function and the second sign function.

8. The processing element of claim 6 , wherein the M-width add-sign instruction specifies the first input operand by specifying a memory location at which the first input operand is located, and wherein the first instruction specifies the second input operand by specifying a memory location at which the second input operand is located.

9. The processing element of claim 6 , wherein the M-width add-sign instruction further specifies a plural set of first input operands and a plural set of second input operands, wherein, in executing the first instruction, the processing element is configured to produce a plural set of result values for the plural set of first input operands and the plural set of second input operands.

10. The processing element of claim 9 , further comprising a bit-packed register, wherein, in executing the M-width add-sign instruction, the processing element is configured to:
store, in the bit-packed register, a plural set of first sign functions corresponding to a plural set of first operand values of the plural set of first input operands; and
store, in the bit-packed register, a plural set of second sign functions corresponding to a plural set of second operand values of the plural set of first input operands.

11. The processing element of claim 9 , wherein the dual data-processing pathway is considered a first dual data-processing pathway, the processing element further comprising:
a second dual data-processing pathway, wherein the second dual data-processing pathway is configured in the same manner as the first dual data-processing pathway.

12. A processing element, comprising:
a dual data-processing pathway configured to:
at a first time, execute a M-width sign instruction that specifies an input operand including a first operand value and a second operand value, and a sign operand including a first sign function and a second sign function, wherein the input operand is one of a plurality of input operands associated with a forward error correction (FEC) encoded signal, wherein, in executing the first instruction, the dual data-processing pathway is configured to, for each respective input operand of the plurality of input operands:
configure a first operational stage to apply the first sign function to the first operand value; and
configure a second operational stage to apply the second sign function to the second operand value; and

at a second time, execute a different instruction to perform a plurality of data-processing operations other than those configured in response to receiving the M-width sign instruction.

13. The processing element of claim 12 , wherein the M-width sign instruction specifies the input operand by specifying a memory location at which the input operand is located, and wherein the first instruction specifies the si

Assignees

• Coherent Logix Inc

Inventors

• Bindloss Keith M
• Dobbs Carl S
• Mezhibovsky Evgeny
• Raza Zahir
• Shelby Kevin A

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title