Self-aligned 3-d epitaxial structures for mos device fabrication
US-2024379453-A1 · Nov 14, 2024 · US
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Aubertine Daniel B patents
Aubertine Daniel B is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Aubertine Daniel B |
| Total patents | 38 |
| First publication | Jan 8, 2015 |
| Latest publication | Nov 14, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Self-aligned 3-D epitaxial structures for MOS device fabrication
US-12046517-B2 · Jul 23, 2024 · US
Self-aligned 3-d epitaxial structures for mos device fabrication
US-2022028747-A1 · Jan 27, 2022 · US
Self-aligned 3-D epitaxial structures for MOS device fabrication
US-11171058-B2 · Nov 9, 2021 · US
Techniques for controlling transistor sub-fin leakage
US-10879241-B2 · Dec 29, 2020 · US
Crystallized silicon carbon replacement material for NMOS source/drain regions
US-10559689-B2 · Feb 11, 2020 · US
Fin sculpting and cladding during replacement gate process for transistor channel applications
US-10403626-B2 · Sep 3, 2019 · US
Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US-10396203-B2 · Aug 27, 2019 · US
Transistor fin formation via cladding on sacrificial core
US-10373977-B2 · Aug 6, 2019 · US
Pre-sculpting of si fin elements prior to cladding for transistor channel applications
US-2019006508-A1 · Jan 3, 2019 · US
Recent patents
Latest publications not already listed above.
Crystallized silicon carbon replacement material for nmos source/drain regions
US-2018374951-A1 · Dec 27, 2018 · US
Enhanced dislocation stress transistor
US-10084087-B2 · Sep 25, 2018 · US
Techniques for controlling transistor sub-fin leakage
US-2018247939-A1 · Aug 30, 2018 · US
Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US-10014412-B2 · Jul 3, 2018 · US
Transistor fin formation via cladding on sacrifical core
US-2018158841-A1 · Jun 7, 2018 · US
High mobility strained channels for fin-based transistors
US-9893149-B2 · Feb 13, 2018 · US
Self-aligned 3-d epitaxial structures for mos device fabrication
US-2018019170-A1 · Jan 18, 2018 · US
Nanowire transistor devices and forming techniques
US-9812524-B2 · Nov 7, 2017 · US
Self-aligned 3-D epitaxial structures for MOS device fabrication
US-9728464-B2 · Aug 8, 2017 · US
Pre-sculpting of si fin elements prior to cladding for transistor channel applications
US-2017222035-A1 · Aug 3, 2017 · US
Enhanced dislocation stress transistor
US-2017222052-A1 · Aug 3, 2017 · US
Enhanced dislocation stress transistor
US-9660078-B2 · May 23, 2017 · US
Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
US-9653584-B2 · May 16, 2017 · US
Fin sculpting and cladding during replacement gate process for transistor channel applications
US-2017133376-A1 · May 11, 2017 · US
Pre-sculpting of si fin elements prior to cladding for transistor channel applications
US-2016308032-A1 · Oct 20, 2016 · US
Nanowire transistor devices and forming techniques
US-2016260802-A1 · Sep 8, 2016 · US
Nanowire transistor devices and forming techniques
US-9343559-B2 · May 17, 2016 · US
Enhanced dislocation stress transistor
US-2016079423-A1 · Mar 17, 2016 · US
High mobility strained channels for fin-based transistors
US-2016071934-A1 · Mar 10, 2016 · US
Enhanced dislocation stress transistor
US-9231076-B2 · Jan 5, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 36 |
| Glass Glenn A | 3 |
| Murthy Anand S | 3 |
| Aubertine Daniel B | 3 |
| Tahoe Res Ltd | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/62 | 18 |
| H10D30/024 | 18 |
| H10D30/751 | 18 |
| H10D62/822 | 15 |
| H10D62/151 | 15 |