High mobility strained channels for fin-based transistors

Patent metadata

Field	Value
Publication number	US-9893149-B2
Application number	US-201514935971-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Jul 27, 2012
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a silicon germanium (SiGe) fin extending therefrom, the fin having a base region and a channel region native to the base region, the base region of the fin below the channel region of the fin, the base region of the fin between first and second regions of shallow trench isolation material, the channel region of the fin between portions of a gate structure, wherein the channel region of the fin is thinner than the base region of the fin;
a cladding layer of germanium on one or more surfaces of the channel region of the fin; and
SiGe source/drain material in source/drain regions adjacent the channel region.

2. The semiconductor device of claim 1 wherein the cladding layer is on multiple sides of the channel region of the fin and the base region of the fin is not cladded with the cladding layer.

3. The semiconductor device of claim 1 further comprising a capping layer between the cladding layer and a gate dielectric layer of the gate structure.

4. The semiconductor device of claim 3 wherein the capping layer is silicon.

5. The semiconductor device of claim 1 wherein the fin is native to the substrate.

6. The semiconductor device of claim 1 wherein the fin is not native to the substrate.

7. A mobile computing system comprising the semiconductor device of claim 1 .

8. A semiconductor device, comprising:
a silicon substrate including a silicon germanium (SiGe) fin extending therefrom, the fin having a channel region, wherein the channel region of the fin is thinner than other portions of the fin;
a cladding layer of germanium on one or more surfaces of the channel region of the fin; and
SiGe source/drain material in source/drain regions adjacent the channel region.

9. The semiconductor device of claim 8 wherein the cladding layer is on multiple sides of the channel region of the fin and the other portions of the fin are not cladded with the cladding layer.

10. The semiconductor device of claim 8 further comprising a capping layer between the cladding layer and a gate dielectric layer of a gate structure.

11. The semiconductor device of claim 10 wherein the capping layer is silicon.

12. The semiconductor device of claim 8 wherein the cladding layer has a thickness of 100 angstroms or less.

13. The semiconductor device of claim 8 wherein the fin comprises 10% to 90% germanium.

14. A semiconductor device, comprising:
a substrate including a silicon or silicon germanium (SiGe) fin extending therefrom, the fin having a channel region, wherein the channel region of the fin is thinner than other portions of the fin;
a cladding layer of germanium on one or more surfaces of the channel region of the fin; and
SiGe source/drain material in source/drain regions adjacent the channel region.

15. The semiconductor device of claim 14 wherein the cladding layer is on multiple sides of the channel region of the fin and the other portions of the fin are not cladded with the cladding layer.

16. The semiconductor device of claim 14 further comprising a capping layer between the cladding layer and a gate dielectric layer of a gate structure.

17. The semiconductor device of claim 16 wherein the capping layer is silicon.

18. The semiconductor device of claim 14 wherein the fin is not native to the substrate.

19. The semiconductor device of claim 14 wherein the fin is native to the substrate.

20. The semiconductor device of claim 19 wherein the fin further includes material that is not native to the substrate.

Assignees

• Intel Corp

Inventors

• Cea Stephen M
• Murthy Anand S
• Glass Glenn A
• Aubertine Daniel B
• Ghani Tahir
• Kavalieros Jack T
• Kotlyar Roza

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L29/1054 Primary

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic