Memory layers at opposing sides of a complementary metal-oxide semiconductor layer
US-2025098179-A1 · Mar 20, 2025 · US
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Murthy Anand S patents
Murthy Anand S holds 28 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 28 |
| Recent patents | 8 |
| First publication | Feb 17, 2015 |
| Latest publication | Mar 20, 2025 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Trim patterning for forming angled transistors
US-2024105798-A1 · Mar 28, 2024 · US
Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions
US-2023207651-A1 · Jun 29, 2023 · US
Integrated circuits with gate plugs to induce compressive channel strain
US-2023207696-A1 · Jun 29, 2023 · US
Integrated circuit structures having metal gate plug landed on dielectric anchor
US-2023197816-A1 · Jun 22, 2023 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Memory layers at opposing sides of a complementary metal-oxide semiconductor layer
US-2025098179-A1 · Mar 20, 2025 · US
Trim patterning for forming angled transistors
US-2024105798-A1 · Mar 28, 2024 · US
Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions
US-2023207651-A1 · Jun 29, 2023 · US
Integrated circuits with gate plugs to induce compressive channel strain
US-2023207696-A1 · Jun 29, 2023 · US
Integrated circuit structures having metal gate plug landed on dielectric anchor
US-2023197816-A1 · Jun 22, 2023 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10D30/6735 | 20 |
| H10D62/121 | 14 |
| H10D64/017 | 13 |
| H10D30/62 | 13 |
| H10D84/853 | 12 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 28 |
| Operations & Transport | 11 |
| Physics | 1 |