Self-aligned 3-D epitaxial structures for MOS device fabrication

Patent metadata

Field	Value
Publication number	US-9728464-B2
Application number	US-201213560513-A
Country	US
Kind code	B2
Filing date	Jul 27, 2012
Priority date	Jul 27, 2012
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

First claim

What is claimed is:

1. A method for forming a fin-based transistor structure, the method comprising:
forming a fin on a substrate, the fin extending from the substrate;
forming shallow trench isolation material on opposing sides of the fin;
recessing the fin to provide a first recess;
forming a substitute fin including strained silicon-germanium (SiGe) in the first recess, the substitute fin comprising a channel of the transistor structure, the substitute fin having a width of less than 30 nanometers, a height of greater than 35 nanometers, and a germanium concentration of greater than 40%; and
forming a gate over three surfaces of the substitute fin to form a tri-gate structure, wherein the substitute fin includes strained SiGe throughout all of the substitute fin after the gate is formed over three surfaces of the substitute fin.

2. The method of claim 1 wherein recessing the fin to provide a first recess comprises:
masking at least a portion above the substrate so as to leave the fin unmasked; and
recessing the unmasked fin to provide the first recess.

3. The method of claim 2 further comprising:
planarizing the portion above the substrate, wherein said planarizing includes removing masking material from the portion above the substrate.

4. The method of claim 3 further comprising:
masking the substitute fin so as to leave an unmasked sacrificial fin;
recessing the unmasked sacrificial fin to provide a second recess; and
forming a substitute fin of a non-SiGe material in the second recess.

5. The method of claim 4 wherein at least one common horizontal plane cuts through respective channels of the SiGe substitute fin and the non-SiGe substitute fin.

6. The method of claim 4 wherein there is no common horizontal plane that cuts through respective channels of the SiGe and non-SiGe substitute fins.

7. The method of claim 4 wherein the non-SiGe substitute fin is a substitute fin including III-V semiconductor material.

8. The method of claim 7 wherein the SiGe substitute fin is configured for PMOS and the III-V substitute fin is configured for NMOS.

9. The method of claim 4 further comprising:
planarizing the non-SiGe substitute fin, wherein said planarizing includes removing masking material over the SiGe substitute fin.

10. The method of claim 1 wherein the strained SiGe included in the substitute fin is substantially defect free.

11. The method of claim 1 further comprising:
forming source/drain regions adjacent to the channel of the transistor structure.

12. The method of claim 1 wherein the strained SiGe included in the substitute fin includes a germanium concentration of 100%, such that the material included in the substitute fin is germanium.

13. The method of claim 1 wherein the channel includes one of n-type dopant and p-type dopant.

14. An integrated circuit formed by the method of claim 1 .

15. An integrated circuit (IC) comprising:
a first substitute fin including strained silicon-germanium (SiGe) throughout all of the first substitute fin, the first substitute fin extending from a substrate and comprising a transistor channel area, the first substitute fin having a width of less than 30 nanometers, a height of greater than 35 nanometers, and a germanium concentration of greater than 40%;
a second fin extending from the substrate and comprising a transistor channel area; and
a gate stack over three surfaces of the first substitute fin to form three gates.

16. The IC of claim 15 wherein the second fin is a substitute fin including III-V semiconductor material.

17. The IC of claim 15 wherein the second fin does not include SiGe material.

18. The IC of claim 17 wherein the second fin is also a substitute fin.

19. The IC of claim 17 wherein the second fin is not a substitute fin.

20. The IC of claim 15 further comprising:
shallow trench isolation material on opposing sides of each of the first and second fins.

21. The IC of claim 15 wherein at least one common horizontal plane cuts through both the transistor channel area of the first substitute fin and the transistor channel area of the second fin.

22. The IC of claim 15 wherein there is no common horizontal plane that cuts through both the transistor channel area of the first substitute fin and the transistor channel area of the second fin.

23. The IC of claim 15 wherein the transistor channel area of the first substitute fin is configured for PMOS and the transistor channel area of the second fin is configured for NMOS.

24. The IC of claim 15 further comprising:
source/drain regions adjacent to each transistor channel area.

25. The IC of claim 15 wherein the strained SiGe included in the first substitute fin is substantially defect free.

26. A computing system comprising the integrated circuit of claim 15 .

27. An integrated circuit (IC) comprising:
a first substitute fin including strained silicon-germanium (SiGe) throughout all of the first substitute fin, the first substitute fin extending from a substrate and comprising a channel area, the first substitute fin having a width of less than 30 nanometers, a height of greater than 35 nanometers, and a germanium concentration of greater than 40%;
a second fin extending from the substrate and comprising a channel area;
shallow trench isolation material on opposing sides of each of the first and second fins;
a gate stack on multiple channel area surfaces of the first and second fins and extending above the shallow trench isolation material so as to provide multi-gates per fin, wherein the gate stack is over three surfaces of the first substitute fin to form three gates; and
source/drain regions adjacent the channel area of the first substitute fin;
wherein at least one common horizontal plane cuts through both the channel area of the first substitute fin and the channel area of the second fin.

28. The IC of claim 27 wherein the second fin does not include SiGe material.

29. The IC of claim 27 wherein the second fin is a substitute fin including III-V semiconductor material.

30. The IC of claim 29 wherein the channel area of the first substitute fin is configured for PMOS and the channel area of the second fin is configured for NMOS.

Assignees

• Glass Glenn A
• Aubertine Daniel B
• Murthy Anand S
• Thareja Gaurav
• Ghani Tahir
• Intel Corp

Inventors

• Glass Glenn A
• Aubertine Daniel B
• Murthy Anand S
• Thareja Gaurav
• Ghani Tahir

Classifications

• H01L21/823814

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L21/823807 Primary

  Electricity · mapped topic

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title