Memory controller management techniques for managing data transfer for memory access operations

Patent metadata

Field	Value
Publication number	US-12561277-B2
Application number	US-202017430611-A
Country	US
Kind code	B2
Filing date	Mar 14, 2020
Priority date	Mar 15, 2019
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
processor circuitry to:
manage data transfer between a cache memory and a high-bandwidth memory for memory access operations directed to the high-bandwidth memory;
facilitate a timer associated with a memory controller to serve as a watchdog timer to track memory accesses to allow high priority memory accesses to execute while delaying low priority memory accesses, wherein the high priority memory accesses are allowed or the low priority memory accesses are delayed based on whether a number of transactions have reached the threshold; and
automatically close a page in the cache memory in response to a determination that a number of transactions to the page has reached the threshold, wherein the page is allowed to remain open when the number of transactions executed to the page are less than the threshold, and wherein the threshold is reduced or increased in response to increased loads on the cache memory or decreased loads on the cache memory, respectively.

2 . The apparatus of claim 1 , wherein the processor circuitry is further to:
initiate a read operation to the high-bandwidth memory in a child process spawned from a parent process; and return a fixed-sized block of data from the high-bandwidth memory when the read operation in the child process hits a memory address of a parent process block write operation.

3 . The apparatus of claim 1 , wherein the processor circuitry is further to:
automatically close a page in the cache memory in response to a determination that a transaction of a specific size has been executed to the page.

4 . The apparatus of claim 1 , wherein the processor circuitry is further to:
monitor a number of memory access request directed to one or more pages of memory; place the memory access requests in a first queue ranked in order from a highest number of memory requests directed to a memory page to a lowest number of memory requests directed to a memory page; and execute the memory requests in order of their respective ranking in the first queue.

5 . The apparatus of claim 4 , wherein the processor circuitry is further to:
remove a memory request from the first queue upon expiration of a watchdog timer for the memory request; and place the memory request in a second queue for execution.

6 . The apparatus of claim 5 , wherein the processor circuitry comprises graphics processor circuitry or application processor circuitry.

7 . A method comprising:
managing, by a processor of a computing device, data transfer between a cache memory and a high-bandwidth memory for memory access operations directed to the high-bandwidth memory; facilitating a timer associated with a memory controller to serve as a watchdog timer to track memory accesses to allow high priority memory accesses to execute while delaying low priority memory accesses, wherein the high priority memory accesses are allowed or the low priority memory accesses are delayed based on whether a number of transactions have reached the threshold; and automatically close a page in the cache memory in response to a determination that a number of transactions to the page has reached the threshold, wherein the page is allowed to remain open when the number of transactions executed to the page are less than the threshold, and wherein the threshold is reduced or increased in response to increased loads on the cache memory or decreased loads on the cache memory, respectively.

8 . The method of claim 7 , further comprising positioning a random number generator to execute proximate to the cache memory.

9 . The method of claim 8 , wherein the random number generator is positioned to execute proximate to an entity which is to consume the random numerical data.

10 . The method of claim 7 , further comprising:
configuring the cache memory by writing one or more metadata codes which map to one or more cache lines in the cache memory.

11 . The method of claim 7 , further comprising:
monitoring a number of memory access request directed to one or more pages of memory; placing the memory access requests in a first queue ranked in order from a highest number of memory requests directed to a memory page to a lowest number of memory requests directed to a memory page; and executing the memory requests in order of their respective ranking in the first queue.

12 . The method of claim 11 , further comprising:
removing a memory request from the first queue upon expiration of a watchdog timer for the memory request; and placing the memory request in a second queue for execution.

13 . The method of claim 12 , wherein the processor comprises a graphics processor or an application processor.

14 . At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
managing data transfer between a cache memory and a high-bandwidth memory for memory access operations directed to the high-bandwidth memory; facilitating a timer associated with a memory controller to serve as a watchdog timer to track memory accesses to allow high priority memory accesses to execute while delaying low priority memory accesses, wherein the high priority memory accesses are allowed or the low priority memory accesses are delayed based on whether a number of transactions have reached the threshold; and automatically close a page in the cache memory in response to a determination that a number of transactions to the page has reached the threshold, wherein the page is allowed to remain open when the number of transactions executed to the page are less than the threshold, and wherein the threshold is reduced or increased in response to increased loads on the cache memory or decreased loads on the cache memory, respectively.

15 . The non-transitory computer-readable medium of claim 14 , wherein the operations further comprise positioning a random number generator to execute proximate to the cache memory.

16 . The non-transitory computer-readable medium of claim 15 , wherein the random number generator is positioned to execute proximate to an entity which is to consume the random numerical data.

17 . The non-transitory computer-readable medium of claim 14 , wherein the operations further comprise:
configuring the cache memory by writing one or more metadata codes which map to one or more cache lines in the cache memory.

18 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise:
monitoring a number of memory access request directed to one or more pages of memory; placing the memory access requests in a first queue ranked in order from a highest number of memory requests directed to a memory page to a lowest number of memory requests directed to a memory page; and executing the memory requests in order of their respective ranking in the first queue.

19 . The non-transitory computer-readable medium of claim 18 , wherein the operations further comprise:
removing a memory request from the first queue upon expiration of a watchdog timer for the memory request; and placing the memory request in a second queue for execution.

20 . The non-transitory computer-readable medium of claim 19 , wherein the computing device comprises one or more processors comprising one or more graphics processors or one or more application processors.

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Anantaraman Aravindh
• Ould-Ahmed-Vall Elmoustapha
• Andrei Valentin
• Galoppo Von Borries Nicolas
• George Varghese
• Koker Altug
• Macpherson Mike
• Maiyuran Subramaniam
• Ray Joydeep
• Pappu Lakshminarayana
• Garcia Guadalupe

Classifications

• G06F13/1626

  by reordering requests · CPC title

• G06T15/06

  Ray-tracing · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title