Cache structure and utilization

Patent metadata

Field	Value
Publication number	US-2024411717-A1
Application number	US-202418738785-A
Country	US
Kind code	A1
Filing date	Jun 10, 2024
Priority date	Mar 15, 2019
Publication date	Dec 12, 2024
Grant date	—

Abstract

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

First claim

1 - 20 . (canceled)

21 . An apparatus comprising:
one or more processors including a graphics processing unit (GPU); a memory for storage of data for processing by the one or more processors; and wherein the one or more processors includes a cache to cache data from the memory for use by the one or more processors; and wherein the apparatus is to provide for processing of the cache, including:
monitoring operation of the cache,
detecting a low activity period in operation of the cache,
identifying one or more cache lines as dirty based at least in part on the monitoring, and
scrubbing the identified one or more cache lines prior to allocation of the one or more cache lines for fetched data.

22 . The apparatus of claim 21 , wherein the cache includes recently used (LRU) information, wherein monitoring operation of the cache includes monitoring a state of the LRU information.

23 . The apparatus of claim 21 , wherein scrubbing the identified one or more cache lines includes writing data from the one or more cache lines back to a source.

24 . The apparatus of claim 21 , wherein processing of the cache further includes:
identifying one or more caches lines for pre-eviction based at least in part on the monitoring; and evicting data from the one or more cache lines prior to allocation of the one or more cache lines for fetched data.

25 . The apparatus of claim 24 , wherein:
monitoring operation of the cache includes detecting an eviction pattern for cache lines in the GPU cache; and identifying the one or more cache lines for pre-eviction includes identifying cache lines based on the detected eviction pattern.

26 . The apparatus of claim 21 , wherein the apparatus is further to provide for receiving and handling read requests for the cache following processing of the cache.

27 . The apparatus of claim 21 , wherein cache is a GPU cache.

28 . The apparatus of claim 21 , wherein the cache is one of an L2 cache or an L3 cache.

29 . One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
monitoring operation of a cache in a computing system, the computing system including one or more processors including a graphics processing unit (GPU); detecting a low activity period in operation of the cache; identifying one or more cache lines as dirty based at least in part on the monitoring; and scrubbing the identified one or more cache lines prior to allocation of the one or more cache lines for fetched data.

30 . The one or more storage mediums of claim 29 , wherein the cache includes recently used (LRU) information, wherein monitoring operation of the cache includes monitoring a state of the LRU information.

31 . The one or more storage mediums of claim 29 , wherein scrubbing the identified one or more cache lines includes writing data from the one or more cache lines back to a source.

32 . The one or more storage mediums of claim 29 , wherein the instructions further include instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
identifying one or more caches lines for pre-eviction based at least in part on the monitoring; and evicting data from the one or more cache lines prior to allocation of the one or more cache lines for fetched data.

33 . The one or more storage mediums of claim 32 , wherein:
monitoring operation of the cache includes detecting an eviction pattern for cache lines in the GPU cache; and identifying the one or more cache lines for pre-eviction includes identifying cache lines based on the detected eviction pattern.

34 . The one or more storage mediums of claim 29 , wherein the instructions further include instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
receiving and handling read requests for the cache.

35 . A method comprising:
monitoring operation of a cache in a computing system, the computing system including one or more processors including a graphics processing unit (GPU); detecting a low activity period in operation of the cache; identifying one or more cache lines as dirty based at least in part on the monitoring; and scrubbing the identified one or more cache lines prior to allocation of the one or more cache lines for fetched data.

36 . The method of claim 35 , wherein the cache includes recently used (LRU) information, wherein monitoring operation of the cache includes monitoring a state of the LRU information.

37 . The method of claim 35 , wherein scrubbing the identified one or more cache lines includes writing data from the one or more cache lines back to a source.

38 . The method of claim 35 , further comprising:
identifying one or more caches lines for pre-eviction based at least in part on the monitoring; and evicting data from the one or more cache lines prior to allocation of the one or more cache lines for fetched data.

39 . The method of claim 38 , wherein:
monitoring operation of the cache includes detecting an eviction pattern for cache lines in the GPU cache; and identifying the one or more cache lines for pre-eviction includes identifying cache lines based on the detected eviction pattern.

40 . The method of claim 35 , further comprising:
receiving and handling read requests for the cache.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Striramassarma Lakshminarayanan
• Anantaraman Aravindh
• Andrei Valentin
• Appu Abhishek R
• Coleman Sean
• George Varghese
• K Pattabhiraman
• Macpherson Mike
• Maiyuran Subramaniam
• Ould-Ahmed-Vall Elmoustapha
• Ranganathan Vasanth
• Ray Joydeep
• S Jayakrishna P
• Surti Prasoonkumar

Classifications

• G06F2212/652

  Page size control · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title