Tensor Register Files
US-2018341483-A1 · Nov 29, 2018 · US
with adaptable data path
with adaptable data path · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F9/3897 |
| Official title | {with adaptable data path} |
| Display label | with adaptable data path |
| Total patents | 246 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 19 |
| 2016 | 13 |
| 2017 | 20 |
| 2018 | 15 |
| 2019 | 18 |
| 2020 | 30 |
| 2021 | 33 |
| 2022 | 28 |
| 2023 | 27 |
| 2024 | 19 |
| 2025 | 21 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Instruction and Logic for Programmable Fabric Hierarchy and Cache
US-2018329724-A1 · Nov 15, 2018 · US
Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
US-10127041-B2 · Nov 13, 2018 · US
Apparatus and method to switch configurable logic units
US-2018307483-A1 · Oct 25, 2018 · US
Vector reduction processor
US-10108581-B1 · Oct 23, 2018 · US
Vector reduction processor
US-2018285316-A1 · Oct 4, 2018 · US
Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and methods
US-9977676-B2 · May 22, 2018 · US
Switchable topology machine
US-2018113838-A1 · Apr 26, 2018 · US
Modifications to a stream processing topology during processing of a data stream
US-2017351633-A1 · Dec 7, 2017 · US
Incremental scheduler for out-of-order block isa processors
US-2017315813-A1 · Nov 2, 2017 · US
Out-of-order block-based processors and instruction schedulers
US-2017315814-A1 · Nov 2, 2017 · US
Parallel instruction scheduler for block isa processor
US-2017315812-A1 · Nov 2, 2017 · US
Hybrid block-based processor and custom function blocks
US-2017315815-A1 · Nov 2, 2017 · US
Scalable compute fabric
US-9798551-B2 · Oct 24, 2017 · US
System and method for managing pipelines in reconfigurable integrated circuit architectures
US-9722614-B2 · Aug 1, 2017 · US
Scalable compute fabric
US-2017206113-A1 · Jul 20, 2017 · US
Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods
US-9684509-B2 · Jun 20, 2017 · US
Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
US-2017161036-A1 · Jun 8, 2017 · US
Processor with an expandable instruction set architecture for dynamically configuring execution resources
US-2017161067-A1 · Jun 8, 2017 · US
Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
US-2017161037-A1 · Jun 8, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F9/3897?
- CPC G06F9/3897 is the Cooperative Patent Classification code for “with adaptable data path.”
- How many patents are filed under CPC G06F9/3897 (with adaptable data path)?
- Our database includes 246 publications tagged with this CPC code.
- Is patent activity under CPC G06F9/3897 growing?
- Publication counts under this code: 19 in 2024 vs 21 in 2025 (latest complete years).