System and method for managing pipelines in reconfigurable integrated circuit architectures

Patent metadata

Field	Value
Publication number	US-9722614-B2
Application number	US-201414553754-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a reconfigurable logic array comprising a plurality of cells electrically coupled via an interconnect and configured to perform an identified task;
one or more of the plurality of cells designated as an active cell configured with a sensor that identifies a back pressure condition at an interface coupled to the active cell, wherein the active cell communicates a do-not-end-step signal in response to the back pressure condition;
a controller electrically coupled to the interconnect and arranged to receive the do-not-end step signal and suspend execution of the identified task in the reconfigurable logic array_in response to a global counter of a number of iterations to perform the identified task.

2. The integrated circuit of claim 1 , wherein the controller is further arranged to suspend execution in the reconfigurable logic array upon receipt of an interrupt request.

3. The integrated circuit of claim 1 , further comprising:
a set of local memory interface cells distributed throughout the reconfigurable logic array, the local memory interface cells arranged to forward a signal responsive to a condition of a volatile memory element coupled to the reconfigurable logic array.

4. The integrated circuit of claim 3 , wherein the controller upon receipt of the signal responsive to the condition of the volatile memory element suspends execution of the reconfigurable logic array.

5. The integrated circuit of claim 4 , wherein the condition of the volatile memory element indicates that data needs to be written to the volatile memory element and a write request is indicated.

6. The integrated circuit of claim 1 , wherein the controller generates and distributes
a phase-age signal and a pipeline-phase signal to the active cell in response to the global counter.

7. The integrated circuit of claim 6 , wherein the controller updates the global counter and communicates an end-of-step signal at an appropriate time to elements in the reconfigurable logic array to control when data gets written to internal registers.

8. The integrated circuit of claim 1 , wherein the active cell is a source configured to transmit the do-not-end-step signal at an appropriate time before source buffered data is exhausted.

9. The integrated circuit of claim 1 , wherein the active cell is a sink configured to transmit the do-not-end-step signal at an appropriate time before a first-in first-out buffer reaches capacity.

10. The integrated circuit of claim 1 , wherein the controller receives an input responsive to the number of iterations to complete the identified task.

11. The integrated circuit of claim 10 , wherein the controller communicates the number of iterations to at least one of a source and a sink prior to entering a loop of instructions.

12. The integrated circuit of claim 1 , wherein the
interconnect includes a switch box arranged to receive a write-stage configuration.

13. The integrated circuit of claim 12 , wherein the switch box includes at least one register responsive to a write-stage influence indicator, wherein when the write-stage indicator is set, a write enable control for the register is disabled.

14. The integrated circuit of claim 13 , wherein a subset of registers is associated with the write-stage influence indicator.

15. A method for managing a reconfigurable logic array in a computing device, the method comprising:
identifying at least one task to be performed by a reconfigurable logic array comprising a plurality of cells electrically coupled via an interconnect, wherein a number of loop iterations to complete the at least one task is known;
receiving, with a controller, a do-not-end-step signal responsive to a back pressure condition identified by an active cell of the reconfigurable logic array;
using the controller to generate an end-of-step signal before a change in the back pressure condition based on a global counter associated with the number of loop iterations; and
broadcasting the end-of-step signal.

16. The method of claim 15 , wherein the active cell includes at least one selected from the group consisting of a source, a sink, and a local memory interface.

17. The method of claim 16 , wherein the local memory interface cells are arranged to forward a signal responsive to a condition of a volatile memory element coupled to the reconfigurable logic array.

18. The method of claim 17 , wherein the signal responsive to the condition of the volatile memory element indicates that data needs to be written to the volatile memory element and a write request is indicated.

19. The method of claim 17 , wherein the signal responsive to the condition of the volatile memory element directs the controller to suspend execution with the reconfigurable logic array.

20. The method of claim 15 , further comprising:
receiving an interrupt request at the controller; and
responding to the interrupt request by using the controller to suspend execution with the reconfigurable logic array.

21. The method of claim 20 , wherein the interrupt request directs the reconfigurable logic array to wait for an external event.

22. The method of claim 15 , further comprising:
suspending execution with the reconfigurable logic array until the back pressure condition is cleared.

23. The method of claim 15 , further comprising:
updating the global counter in anticipation of a subsequent pipeline phase transition; and
distributing a phase-age signal and a pipeline-phase signal together with the end-of-step signal.

24. The method of claim 15 , wherein the active cell is a source configured to transmit the do-not-end-step signal at an appropriate time before source buffered data is exhausted.

25. The method of claim 15 , wherein the active cell is a sink configured to transmit the do-not-end-step signal at an appropriate time before a first-in first-out buffer reaches capacity.

26. The method of claim 15 , wherein broadcasting the end-of-step signal comprises communicating the end-of-step signal to elements in the reconfigurable logic array to control when data gets written to a cell memory.

27. The method of claim 26 , further comprising:
waiting for elements in the reconfigurable logic array to identify when data coming from the reconfigurable logic array has to be updated and when output data has to be modified.

28. The method of claim 15 , further comprising:
prior to entering a loop responsive to the at least one task, communicating the number of loop iterations of valid data to a source, a sink and the controller.

29. The method of claim 15 , further comprising:
providing a write-stage configuration to a switch box;
associating a write-stage influence indicator with a register in the switch box;
when the write-stage influence indicator is set, disabling a write-enable control input for the register.

30. The method of claim 29 , wherein disabling the write enable control input is performed in conjunction with filling or flushing the reconfigurable logic array.

Assignees

• Qualcomm Inc

Inventors

• Muir Mark Ian Roy
• Khawam Sami
• Nousias Ioannis

Classifications

• G06F9/3897

  with adaptable data path · CPC title

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• H03K19/017581

  programmable · CPC title

• G06F2212/20

  Employing a main memory using a specific memory technology · CPC title

• H03K19/1776

  for memories · CPC title