Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory, and related vector processing instructions, systems, and methods

Patent metadata

Field	Value
Publication number	US-9684509-B2
Application number	US-201314082073-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Nov 15, 2013
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

First claim

What is claimed is:

1. A vector processing engine (VPE) configured to in-flight merge a resultant output vector data sample set generated by at least one execution unit executing a vector processing operation, comprising:
at least one vector data file configured to:
provide an input vector data sample set in at least one input data flow path for a vector processing operation; and
receive at least one merged resultant output vector data sample set from at least one output data flow path to be stored;

the at least one execution unit provided in the at least one input data flow path, the at least one execution unit configured to:
receive the input vector data sample set on the at least one input data flow path; and
execute the vector processing operation on the input vector data sample set to provide the resultant output vector data sample set on the at least one output data flow path; and

at least one merging circuitry configured to:
receive the resultant output vector data sample set;
merge resultant output vector data samples in the received resultant output vector data sample set to provide the at least one merged resultant output vector data sample set without the resultant output vector data sample set being stored in the at least one vector data file, wherein the at least one merging circuitry is configured to merge the resultant output vector data samples by adding the resultant output vector data samples, determining a maximum vector data sample among the resultant output vector data samples, or determining a minimum vector data sample among the resultant output vector data samples;
store the at least one merged resultant output vector data sample set in selected one or more latches among a plurality of latches; and
provide the at least one merged resultant output vector data sample set stored in the selected one or more latches on the at least one output data flow path; and
wherein the at least one merging circuitry further comprises a plurality of parallel selectors corresponding to the plurality of latches, wherein the at least one merging circuitry is configured to control the plurality of selectors to store the at least one merged resultant output vector data sample set in the selected one or more latches among the plurality of latches.

2. The VPE of claim 1 , wherein the at least one vector data file is configured to:
provide the input vector data sample set of a width of the at least one vector data file in the at least one input data flow path for the vector processing operation; and
receive the at least one merged resultant output vector data sample set of the width of the at least one vector data file from the at least one output data flow path to be stored.

3. The VPE of claim 1 , wherein:
the at least one vector data file is further configured to:
provide the input vector data sample set on at least one vector data file output in the at least one input data flow path; and
receive the at least one merged resultant output vector data sample set on at least one vector data file input in the at least one output data flow path;

the at least one execution unit configured to:
receive the input vector data sample set on at least one execution unit input in the at least one input data flow path; and
multiply the input vector data sample set with a code sequence vector data sample set to provide the resultant output vector data sample set on at least one execution unit output in the at least one input data flow path; and

the at least one merging circuitry is further configured to:
receive the resultant output vector data sample set on at least one merging circuitry input in the at least one input data flow path from the at least one execution unit; and
provide the at least one merged resultant output vector data sample set on at least one merging circuitry output in the at least one output data flow path.

4. The VPE of claim 3 , wherein the code sequence vector data sample set comprises at least one CDMA chip code sequence.

5. The VPE of claim 1 , wherein the at least one merging circuitry comprises at least one adder configured to add at least two of the resultant output vector data samples in the resultant output vector data sample set to provide the at least one merged resultant output vector data sample set.

6. The VPE of claim 5 , wherein the at least one adder comprises a plurality of adders provided in an adder tree, each of the plurality of adders configured to provide a plurality of add merged resultant output vector data sample sets each having a different bit width.

7. The VPE of claim 5 , wherein the at least one merging circuitry further comprises a merge selector configured to select one of the at least one of merged resultant output vector data sample sets.

8. The VPE of claim 1 , wherein the at least one merging circuitry comprises at least one maximum vector data sample selector configured to select one of two of the resultant output vector data samples having a maximum vector data value among the two of the resultant output vector data samples to provide the at least one merged resultant output vector data sample set.

9. The VPE of claim 8 , wherein the at least one maximum vector data sample selector comprises a plurality of maximum value data sample selectors each configured to provide a plurality of maximum merged resultant output vector data sample sets each having a different bit width.

10. The VPE of claim 1 , wherein the at least one merging circuitry comprises at least one minimum vector data sample selector configured to select one of two of the resultant output vector data samples having a minimum vector data value among the two of the resultant output vector data samples to provide the at least one merged resultant output vector data sample set.

11. The VPE of claim 10 , wherein the at least one minimum vector data sample selector comprises a plurality of minimum value data sample selectors each configured to provide a plurality of minimum merged resultant output vector data sample sets each having a different bit width.

12. The VPE of claim 1 , wherein the at least one merging circuitry is configurable to be reconfigured based on a programmable merge data path configuration input to selectively merge the resultant output vector data samples.

13. The VPE of claim 12 , wherein the at least one merging circuitry is further configured to be reconfigured based on the programmable merge data path configuration input to selectively merge the resultant output vector data samples on each clock cycle of the VPE to be executed by the at least one execution unit.

14. The VPE of claim 12 , wherein the at least one merging circuitry is further configured to be reconfigured based on the programmable merge data path configuration input to selectively merge the resultant output vector data samples on a next vector instruction to be executed by the at least one execution unit.

15. The VPE of claim 1 , wherein the at least one execution unit is configurable to process different bit widths of input vector data samples from the input vector data sample set based on a programmable input data flow path configuration for the at least one execution unit.

16. The VPE of claim 1 , further comprising:
a crossbar circuitry configured to route the at least one merged resultant output vector data sample set to the selected one or more latches of the plurality of latches such that the crossbar circuitry is configured to allow the at least one merged resultant output vector data sample set to be stacked in the plurality of latches among different iterations of merge

Assignees

• Qualcomm Inc

Inventors

• Khan Raheel

Classifications

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F15/8053

  Vector processors · CPC title

• G06F9/3897

  with adaptable data path · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title