Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory, and related vector processor systems and methods

Patent metadata

Field	Value
Publication number	US-9977676-B2
Application number	US-201314082081-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Nov 15, 2013
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

First claim

What is claimed is:

1. A vector processing engine (VPE) configured to in-flight reorder a resultant output vector data sample set generated by at least one execution unit executing a vector processing operation, comprising:
at least one vector data file configured to: provide a fetched input vector data sample set in at least one input data flow path for the vector processing operation; and receive a reordered resultant output vector data sample set from at least one output data flow path to be stored;
at least one tapped-delay line between the at least one vector data file and the at least one execution unit in the at least one input data flow path, the at least one tapped-delay line configured to:
receive the fetched input vector data sample set from the at least one vector data file; and
shift the fetched input vector data sample set by a vector data sample width in a plurality of pipeline registers for each processing stage among a plurality of processing stages equal to a number of vector processing stages in the vector processing operation, to provide a shifted input vector data sample set for each processing stage among the plurality of processing stages in the at least one input data flow path; and
the at least one tapped-delay line including a plurality of input vector data sample selectors, each of the plurality of input vector data sample selectors assigned to a pipeline register among the plurality of pipeline registers in the at least one tapped-delay line, the plurality of input vector data sample selectors each configured to select among an input vector data sample from the fetched input vector data sample set from the at least one vector data file and an input vector data sample stored in an adjacent pipeline register, to store a shifted input vector data sample in an assigned pipeline register;
the at least one execution unit provided in the at least one input data flow path, the at least one execution unit configured to: receive the shifted input vector data sample set; and execute the vector processing operation on the shifted input vector data sample set to provide the resultant output vector data sample set on the at least one output data flow path; and
at least one reordering circuitry configured to: receive the resultant output vector data sample set on the at least one output data flow path; reorder the resultant output vector data sample set into the reordered resultant output vector data sample set without the resultant output vector data sample set being stored in the at least one vector data file; and provide the reordered resultant output vector data sample set on the at least one output data flow path;
wherein the at least one reordering circuitry further comprises: a first plurality of selectors, each configured to: receive first and second resultant output vector data samples of the resultant output vector data sample set, wherein the first and second resultant output vector data samples are non-adjacent to each other in the resultant output vector data sample set; and select between the first and second resultant output vector data samples and output the selected one of the first and second resultant output vector data samples;
wherein the first plurality of selectors are configured to receive all of the resultant output vector data samples of the resultant output vector data sample set; and a second plurality of selectors, each configured to: receive one of the resultant output vector data samples of the resultant output vector data sample set and the output of one of the first plurality of selectors; and select between the one of the resultant output vector data samples and the output of the one of the first plurality of selectors.

2. The VPE of claim 1 , wherein the at least one vector data file is configured to: provide the input vector data sample set of a width of the at least one vector data file in the at least one input data flow path for the vector processing operation; and receive the reordered resultant output vector data sample set of the width of the at least one vector data file from the at least one output data flow path to be stored.

3. The VPE of claim 1 , wherein:
the at least one vector data file is further configured to: provide the input vector data sample set on at least one vector data file output in the at least one input data flow path; and receive the reordered resultant output vector data sample set on at least one vector data file input in the at least one output data flow path;
the at least one execution unit is further configured to: receive the shifted input vector data sample set on at least one execution unit input in the at least one input data flow path; and execute the vector processing operation on the shifted input vector data sample set to provide the resultant output vector data sample set on at least one execution unit output in the at least one output data flow path; and
the at least one reordering circuitry is further configured to: receive the resultant output vector data sample set on at least one reordering circuitry input in the at least one output data flow path from the at least one execution unit and provide the reordered resultant output vector data sample set on at least one reordering circuitry output in the at least one output data flow path.

4. The VPE of claim 1 , wherein the at least one reordering circuitry is configurable to be reconfigured based on a programmable reordering data path configuration input to selectively reorder the resultant output vector data sample set.

5. The VPE of claim 4 , wherein the at least one reordering circuitry is further configured to be reconfigured based on the programmable reordering data path configuration input to selectively reorder the resultant output vector data sample set on each clock cycle of the VPE to be executed by the at least one execution unit.

6. The VPE of claim 1 , wherein the at least one tapped-delay line comprises:
a shadow tapped-delay line configured to: receive the input vector data sample set from the at least one vector data file in the at least one input data flow path into a shadow plurality of pipeline registers; and
shift the input vector data sample set by the vector data sample width in the shadow plurality of pipeline registers for each processing stage into a primary tapped-delay line to provide the shifted input vector data sample set; and the primary tapped-delay line configured to provide the shifted input vector data sample set in the at least one input data flow path in each processing stage in the plurality of processing stages.

7. The VPE of claim 1 , wherein each of the plurality of input vector data sample selectors is configured to select a plurality of grouped input vector data samples collectively storing an input vector data sample word in a plurality of grouped adjacent pipeline registers, to store a shifted input vector data sample word in a plurality of grouped pipeline registers among the plurality of pipeline registers.

8. The VPE of claim 1 , wherein the at least one tapped-delay line is configurable to be selectively provided in the at least one input data flow path between the at least one vector data file and the at least one execution unit based on a programmable data path configuration input for the at least one tapped-delay line according to a vector instruction to be executed by the at least one execution unit.

9. The VPE of claim 8 , wherein the at least one tapped-delay line is configured to be reconfigured to be selectively provided in the at least one input data flow path based on the programmable data path configuration input for the at least one tapped-delay line according to a next vector instruction to be executed by the at least one execution unit.

Assignees

• Qualcomm Inc

Inventors

• Khan Raheel
• Mujahid Fahad Ali

Classifications

• G06F9/38873

  Iterative single instructions for multiple data lanes [SIMD] · CPC title

• G06F15/8053 Primary

  Vector processors · CPC title

• G06F9/3897

  with adaptable data path · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title