Timing optimization driven by statistical sensitivites

Patent metadata

Field	Value
Publication number	US-9767239-B1
Application number	US-201615298921-A
Country	US
Kind code	B1
Filing date	Oct 20, 2016
Priority date	Oct 20, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

System and methods for achieving a timing closure in a design of an integrated circuit in presence of manufacturing variation. The method includes running a timing engine of a statistical timing analysis tool performing at least one optimization to fix at least one violation of at least one timing quantity at an integrated circuit location. The method includes choosing at least one optimization to apply and finding at least one failing timing quantity, where the quantity is failing due to at least one source of variability which the optimization would impact. The optimization is applied to at least one section of the path leading to the failing timing quantity, where the section contributes to the source of variability. Statistical sensitivity information in canonical form guides the optimization by providing a fully parameterized canonical form of the identified timing violations.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit comprising:
using a computer, running a statistical timing analysis (STA) for identifying timing violations at a location in a circuit design;
for an identified timing violation, determining a failing sensitivity resulting in said timing violation;
using said computer, identifying one or more gates/nets which contribute to the failing sensitivity at the location;
using said computer, receiving and applying a transform comprising a design change on one or more of the gates/nets to reduce sensitivity to a process variable associated with the failing sensitivity at the location and statistically reduce a probability of the failing sensitivity at the location;
using the computer, conduct a further statistical timing analysis for determining whether the timing violation was corrected using said applied transform; and

in response to determining that the timing violation was not corrected, iteratively applying the transform to the one or more gates/nets based on a ranked list ordering of paths associated with the one or more gates/nets until the timing violation is corrected.

2. The method of claim 1 , wherein said identifying one or more gates/nets comprises: tracing a critical path and/or paths of said paths and ranking the one or more gates/nets by contribution to said process variable associated with the failing sensitivity at the location.

3. The method of claim 1 , wherein the determining a failing sensitivity resulting in said timing violation further comprises:
accessing data that maps a relationship between a source of variability of the process variable and how the transform impacts that source of variability.

4. The method of claim 2 , wherein the ranking of a gate/net of the one or more gates/nets is based on a process variable that contributes most to sensitivity at a failing timing violation at the location of said circuit.

5. The method of claim 2 , wherein if it is determined that the timing violation was not completely corrected using said applied transform, the method further comprises: iteratively applying multiple transforms, with each transform applied across each said gates/nets in a ranked order that contributes most to sensitivity at a failing timing point of said circuit.

6. The method of claim 1 , wherein a timing violation is a failed timing quantity selected from the group consisting of: a test slack, a slew, an arrival time, a required arrival time, and a capacitance.

7. The method of claim 6 , further comprising: using the computer to project statistical sensitivity information for said identified timing violation in a canonical form, said canonical form representing a statistical distribution of said process variable contributing to the failed timing quantity for projection to all circuit operation models, wherein a circuit operation model includes modeling using one or more of: a low Vdd voltage, high Vdd, low frequency operation, high frequency operation, metal thickness variation, across-chip variation, thermal effects, temperature variation, and voltage-threshold mistrack.

8. The method of claim 6 , further comprising: determining whether a data test side or a clock test side contributes more to the failing timing quantity at a circuit element; and projecting said statistical sensitivity information for said identified timing violation for that side of the test.

9. An apparatus for manufacturing an integrated circuit comprising:
a hardware processor;
a memory storage device storing instructions, said instructions for configuring the hardware processor to perform a method to:
run a statistical timing analysis (STA) for identifying timing violations at a location in a circuit design;
for an identified timing violation, determine a failing sensitivity resulting in said timing violation;
identify one or more gates/nets which contribute to the failing sensitivity at the location;
receive and apply a transform comprising a design change on one or more of the gates/nets to reduce sensitivity to a process variable associated with the failing sensitivity at the location and statistically reduce a probability of the failing sensitivity at the location;
conduct a further statistical timing analysis for determining whether the timing violation was corrected using said applied transform; and
in response to determining that the timing violation was not corrected, iteratively apply the transform to the one or more gates/nets based on a ranked list ordering of paths associated with the one or more gates/nets until the timing violation is corrected.

10. The apparatus of claim 9 , wherein to identify one or more gates/nets, the hardware processor is further configured to: trace a critical path and/or paths of said paths and ranking the one or more gates/nets by contribution to said process variable associated with the failing sensitivity at the location.

11. The apparatus as claimed in claim 9 , wherein to determine a failing sensitivity resulting in said timing violation, said hardware processor is further configured to:
access data that maps a relationship between a source of variability of the process variable and how the transform impacts that source of variability.

12. The apparatus of claim 10 , wherein the ranking of a gate/net of the one or more gates/nets is based on a process variable that contributes most to sensitivity at a failing timing violation at the location of said circuit.

13. The apparatus of claim 10 , wherein if it is determined that the timing violation was not completely corrected using said applied transform, said hardware processor is further configured to:
iteratively apply multiple transforms, with each transform applied across each said gates/nets in a ranked order that contributes most to sensitivity at a failing timing point of said circuit.

14. The apparatus of claim 9 , wherein a timing violation is a failed timing quantity selected from the group consisting of: a test slack, a slew, an arrival time, a required arrival time, and a capacitance.

15. The apparatus of claim 14 , wherein said hardware processor is further configured to:
project statistical sensitivity information for said identified timing violation in a canonical form, said canonical form representing a statistical distribution of said process variable contributing to the failed timing quantity and projected on one or more circuit operation models, wherein a circuit operation model includes modeling using one or more of: a low Vdd voltage, high Vdd, low frequency operation, high frequency operation, metal thickness variation, across-chip variation, thermal effects, temperature variation, and voltage-threshold mistrack.

16. A computer program product comprising:
a non-transitory computer readable media embodying a program of instructions executable by a processing unit for achieving timing closure in a design of an integrated circuit in presence of manufacturing variations, the program of instructions, when executing, performing a method comprising:
running a statistical timing analysis (STA) for identifying timing violations at a location in a circuit design;
for an identified timing violation, determining a failing sensitivity resulting in said timing violation;
identifying one or more gates/nets which contribute to the failing sensitivity at the location;
receiving and applying a transform comprising a design change on one or more of the gates/nets to reduce sensitivity to a process variable associated with the failing sensitivity at the location and statistically reduce a probability of the f

Assignees

• IBM

Inventors

• Buck Nathan C
• Foreman Eric A
• Hemmett Jeffrey G
• Kalafala Kerim
• Schaeffer Gregory M
• Shuma Stephen G
• Venkateswaran Natesan
• Visweswariah Chandramouli
• Zolotov Vladimir

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/30

  Circuit design · CPC title