Method and apparatus for master-clone optimization during circuit analysis

Patent metadata

Field	Value
Publication number	US-9639644-B1
Application number	US-201514606559-A
Country	US
Kind code	B1
Filing date	Jan 27, 2015
Priority date	Jan 27, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical library has internal boundary pins that correspond to the external boundary pins of the target block. The target block is represented as a single block netlist and the block netlist is optimized with respect to the first macro. The steps may be repeated with respect to a master and clone(s) on the same integrated circuit enabling a single block netlist to be optimized for multiple instances of the same design IP.

First claim

What is claimed is:

1. A computer-implemented method for optimizing a circuit design stored in a computer memory, the method comprising:
identifying a target block with an external boundary and external boundary pins in an integrated circuit design;
converting an area outside the target block into a first macro, wherein the first macro has a physical library and a timing library, wherein the physical library represents physical attributes of the area outside the target block including an internal boundary that corresponds to the external boundary of the target block and internal boundary pins that correspond to the external boundary pins of the target block, wherein the timing library represents the timing information of the area outside the target block;
representing the target block as a netlist;
using a computer, optimizing timing characteristics of the netlist with respect to the first macro, wherein optimizing is performed by modifying the netlist to include additional buffers, repeaters, or by re zing gates within a net;
wherein the identifying and converting steps are performed with both a master and a clone as the target block forming a first macro and a second macro, and both the master and clone are represented by a netlist in the representing step, and the netlist is optimized with respect to both the first and second macro in the optimizing step; and
wherein the optimizing step further comprises defining a first mode/corner definition for a first timing library of the first macro and a second mode/corner definition for a second timing library of the second macro and combining the first mode/corner definition and the second mode/corner definition into a single multi-mode multi-corner definition and optimizing the block netlist using the multi-mode multi-corner definition.

2. The method of claim 1 , wherein the identifying and converting steps are performed with both a first piece of design IP and a second identical piece of design IP as the target block forming a first macro and a second macro, and both the first piece of design IP and the second piece of design IP are represented by a netlist in the representing step, and the block netlist is optimized with respect to both the first and second macro in the optimizing step.

3. The method of claim 1 , wherein the first macro is a donut macro.

4. The method of claim 1 , wherein the physical library is a cloud library.

5. The method of claim 1 , wherein the physical library includes information that corresponds to the external boundary of the integrated circuit and the information that corresponds to the external boundary of the integrated circuit is not used during the optimizing step.

6. The method of claim 1 , wherein the area outside the target block corresponds to the entire area of the integrated circuit outside the target block.

7. The method of claim 1 implemented as part of a ReverseILM analysis.

8. The method of claim 1 , wherein the optimizing step optimizes the timing of the block netlist.

9. The method of claim 2 , wherein the master and clone are both processor cores.

10. The method of claim 1 , wherein the optimizing step optimizes a property selected from the group consisting of performance, power and area.

11. A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for optimizing a circuit design stored in a computer memory comprising:
identifying a target block with an external boundary and external boundary pins in an integrated circuit design;
converting an area outside the target block into a first macro, wherein the first macro has a physical library and a timing library, wherein the physical library represents physical attributes of the area outside the target block including an internal boundary that corresponds to the external boundary of the target block and internal boundary pins that correspond to the external boundary pins of the target block, wherein the timing library represents the timing information of the area outside the target block;
representing the target block as a netlist; and,
using a computer, optimizing timing characteristics of the netlist with respect to the first macro, wherein optimizing is performed by modifying the netlist to include additional buffers, repeaters, or by re zing gates within a net;
wherein the identifying and converting steps are performed with both a master and a clone as the target block forming a first macro and a second macro, and both the master and clone are represented by a netlist in the representing step, and the block netlist is optimized with respect to both the first and second macro in the optimizing step; and
wherein the optimizing step further comprises defining a first mode/corner definition for a first timing library of the first macro and a second mode/corner definition for a second timing library of the second macro and combining the first mode/corner definition and the second mode/corner definition into a single multi-mode multi-corner definition and optimizing the block netlist using the multi-mode multi-corner definition.

12. The medium of claim 11 , wherein the identifying and converting steps are performed with both a first piece of design IP and a second identical piece of design IP as the target block forming a first macro and a second macro, and both the first piece of design IP and the second piece of design IP are represented by a netlist in the representing step, and the block netlist is optimized with respect to both the first and second macro in the optimizing step.

13. The medium of claim 11 , wherein the first macro is a donut macro.

14. The medium of claim 11 , wherein the physical library is a cloud library.

15. The medium of claim 11 , wherein the physical library includes information that corresponds to the external boundary of the integrated circuit and the information that corresponds to the external boundary of the integrated circuit is not used during the optimizing step.

16. The medium of claim 11 , wherein the area outside the target block corresponds to the entire area of the integrated circuit outside the target block.

17. The medium of claim 11 implemented as part of a ReverseILM analysis.

18. The medium of claim 11 , wherein the optimizing step optimizes the timing of the block netlist.

19. The medium of claim 14 wherein the master and clone are both processor cores.

20. The medium of claim 11 , wherein the optimizing step optimizes a property selected from the group consisting of performance, power and area.

21. A computer-implemented method for optimizing a circuit design stored in a computer memory, the method comprising:
identifying a master having external boundary pins and a clone having external boundary pins in an integrated circuit design having input output pins;
converting an area outside the master into a first macro with internal boundary pins corresponding to the external boundary pins of the master and external boundary pins corresponding to the input output pins of the integrated circuit;
converting an area outside the clone into a second macro with internal boundary pins corresponding to the external boundary pins of the clone and external boundary pins corresponding to the chip input output pins;
representing both the master and the clone with a netlist; and,
using a computer, optimizing timing characteristics of the netlist with respect to the first macro and the second macro, wherein optimizing is performed by modifying the netlist to inclu

Assignees

• Cadence Design Systems Inc

Inventors

• Liu Dongzi
• Pan Deng

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5045 Primary

  Physics · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/30

  Circuit design · CPC title