Block-level code coverage in simulation of circuit designs

Patent metadata

Field	Value
Publication number	US-9600613-B1
Application number	US-201514633417-A
Country	US
Kind code	B1
Filing date	Feb 27, 2015
Priority date	Feb 27, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.

First claim

What is claimed is:

1. A method, comprising:
Identifying, in a circuit design, code blocks for which execution of operations indicated by the code blocks is conditioned on a value of one or more of a set of configuration parameters of the circuit design;
determining, for each identified code block, a respective expression indicating whether or not the operations indicated by the code block will be executed for different sets of values of the set of configuration parameters; and
for a first set of values of the different sets of values:
generating, using a simulation model generator that removes code blocks for which operations indicated by the code blocks are not executed, a first simulation model of the circuit design configured with the first set of values for the configuration parameters;
executing the first simulation model;
evaluating the determined expressions to determine whether or not each identified code block was realized in the simulation of the circuit design configured with the first set of values for the configuration parameters; and
storing a first set of data indicative of ones of identified code blocks determined to be realized in the simulation of the circuit design configured with the first set of values.

2. The method of claim 1 , further comprising evaluating, in response to executing the simulation model, the first set of data to determine a subset of code blocks that were not included in the simulation model of the circuit design with the first set of values.

3. The method of claim 2 , further comprising:
determining, using the determined respective expressions, a second set of values of the configuration parameters for which operations indicated by one or more of the subset of code blocks will be executed in a simulation of the circuit design configured with the second set of values for the configuration parameters;
generating, using a simulation model generator, a second simulation model of the circuit design configured with the second set of values for the configuration parameters; and
executing the second simulation model.

4. The method of claim 3 , further comprising storing a second set of data indicative of the ones of identified code blocks that were realized in the second simulation model of the circuit design.

5. The method of claim 1 , wherein:
the first simulation model includes a plurality of code statements; and
the method further comprises storing, in response to executing the first simulation model, a respective set of data indicating code statements of the first simulation model that were not executed in the executing of the first simulation model.

6. The method of claim 1 , wherein:
the respective expression for at least one identified code block includes a plurality of code statements; and
the method further comprises determining which of the plurality of code statements are executed in the evaluating of the respective expression.

7. The method of claim 1 , further comprising determining, using the expressions determined for the identified code blocks, a subset of the different sets of values of the set of configuration parameters for which operations described by each of the identified code blocks will be executed at least once in simulating the circuit design for each of the subset of the different sets of values.

8. The method of claim 7 , further comprising determining, using the expressions determined for the identified code blocks, a smallest subset of the different sets of values of the set of configuration parameters for which each of the identified code blocks will be executed at least once in simulating the circuit design for each of the subset of the different sets of values.

9. The method of claim 1 , wherein the identifying code blocks of the circuit design includes:
traversing the circuit design to identify configuration parameters; and
identifying portions of code for which execution of operations described by the portions of code is conditioned on one or more of the identified configuration parameters.

10. A method, comprising:
Identifying, in a circuit design, code blocks for which execution is conditioned on a value of one or more of a set of configuration parameters;
determining, for each identified code block, a respective expression indicating whether or not the code block will be executed in simulation of the circuit design for different sets of values of the set of configuration parameters;
selecting a subset of the different sets of values as a function of the determined expressions; and
for each set of values in the subset:
generating, using a simulation model generator that removes code blocks for which operations indicated by the code blocks are not executed, a simulation model of the circuit design configured with the set of values for the configuration parameters; and
executing the simulation model to simulate the circuit design configured with the set of values of the configuration parameters.

11. The method of claim 10 , wherein the subset of the different sets of values includes, for each of the identified code blocks, at least one set of values for which operations described by the code block will be executed in simulation of the circuit design using the set of values of the configuration parameters.

12. The method of claim 10 , wherein the subset of the different sets of values is the smallest subset of the different sets of values wherein, for each of the identified code blocks, at least one set of values for which operations described by the code block will be executed in simulation of the circuit design using the set of values of the configuration parameters.

13. The method of claim 10 , wherein the generating of the simulation model for a set of values in the subset includes:
compiling the circuit design with configuration parameters set to the set of values;
removing code blocks from the compiled circuit design for which operations indicated by the code blocks will not be executed in simulation of the circuit design with configuration parameters set to the set of values; and
generating the simulation model from the compiled circuit design.

14. The method of claim 10 , wherein:
the simulation model includes a plurality of code statements; and
the method further comprises identifying, in response to executing the simulation model, code statements of the simulation model whose described operations were not executed in the executing of the simulation model.

15. The method of claim 10 , wherein:
the respective expression for at least one identified code block includes a plurality of code statements; and
the method further comprises determining which of the plurality of code statements are executed in the evaluating of the respective expression.

16. The method of claim 10 , wherein the identifying code blocks of the circuit design includes:
traversing the circuit design to identify configuration parameters; and
identifying portions of code whose execution is conditioned on one or more of the identified configuration parameters.

17. A system, comprising:
one or more processors; and
a memory arrangement coupled to the one or more processors, wherein the memory arrangement is configured with instructions that when executed by the one or more processors cause the one or more processors to perform operations including:
identifying, in a circuit design, code blocks for which execution is conditioned on a value of one or more of a set of configuration parameters of the circuit design;
determining, for each identified code block, a respective expression indicat

Assignees

• Xilinx Inc

Inventors

• Corbett Kyle

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F17/5054

  Physics · mapped topic

• G06F17/5045

  Physics · mapped topic