System on chip and method of operating a system on chip
US-9529745-B2 · Dec 27, 2016 · US
using combination of interrupt and burst mode transfer
using combination of interrupt and burst mode transfer · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F13/32 |
| Official title | using combination of interrupt and burst mode transfer |
| Display label | using combination of interrupt and burst mode transfer |
| Total patents | 208 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 37 |
| 2016 | 29 |
| 2017 | 29 |
| 2018 | 20 |
| 2019 | 18 |
| 2020 | 14 |
| 2021 | 15 |
| 2022 | 6 |
| 2023 | 14 |
| 2024 | 6 |
| 2025 | 16 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Service processor (SP) initiated data transaction with bios utilizing interrupt
US-9529750-B2 · Dec 27, 2016 · US
Information processor with tightly coupled smart memory unit
US-2016321204-A1 · Nov 3, 2016 · US
Live updates for virtual machine monitor
US-2016313986-A1 · Oct 27, 2016 · US
Coalescing stages in a multiple stage completion sequence
US-9465681-B2 · Oct 11, 2016 · US
Method and apparatus for delivering MSI-X interrupts through non-transparent bridges to computing resources in PCI-express clusters
US-9465760-B2 · Oct 11, 2016 · US
Technologies for moderating packet ingress interrupt generation
US-9455922-B2 · Sep 27, 2016 · US
Command queue for communication bus
US-2016224490-A1 · Aug 4, 2016 · US
Transmitting inter-processor interrupt messages by privileged virtual machine functions
US-2016224484-A1 · Aug 4, 2016 · US
Information processor with tightly coupled smart memory unit
US-9400760-B2 · Jul 26, 2016 · US
Data coherency model and protocol at cluster level
US-9383932-B2 · Jul 5, 2016 · US
I2C controller register, control, command and R/W buffer queue logic
US-9336167-B2 · May 10, 2016 · US
Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
US-9336168-B2 · May 10, 2016 · US
Methods and systems for accessing storage using a network interface card
US-2016124880-A1 · May 5, 2016 · US
Caching methods and systems using a network interface card
US-2016127493-A1 · May 5, 2016 · US
Logical-to-physical block mapping inside the disk controller: accessing data objects without operating system intervention
US-2016098367-A1 · Apr 7, 2016 · US
Live updates for virtual machine monitor
US-9292332-B1 · Mar 22, 2016 · US
System and method for input/output acceleration device having storage virtual appliance (SVA) using root of PCI-E endpoint
US-9262197-B2 · Feb 16, 2016 · US
Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes
US-2016011997-A1 · Jan 14, 2016 · US
Service processor (sp) initiated data transaction with bios utilizing interrupt
US-2016011880-A1 · Jan 14, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F13/32?
- CPC G06F13/32 is the Cooperative Patent Classification code for “using combination of interrupt and burst mode transfer.”
- How many patents are filed under CPC G06F13/32 (using combination of interrupt and burst mode transfer)?
- Our database includes 208 publications tagged with this CPC code.
- Is patent activity under CPC G06F13/32 growing?
- Publication counts under this code: 6 in 2024 vs 16 in 2025 (latest complete years).