Service processor (SP) initiated data transaction with bios utilizing interrupt

Patent metadata

Field	Value
Publication number	US-9529750-B2
Application number	US-201414330161-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first system management interface (SMI) message, and sends the first SMI message to the host computer to initiate a data transaction. The OS, in response to the first SMI message, execute a SMI handler in a system management random access memory (SMRAM) area at the CPU to enter a system management mode (SMM). The SMI handler then sends the notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.

First claim

What is claimed is:

1. A system, comprising:
a service processor (SP), comprising a processor, a non-volatile memory, and a communication interface, wherein the non-volatile memory stores computer executable code configured to, when executed at the processor,
generate a first system management interrupt (SMI) message, and send the first SMI message to a host computer;
receive, via the communication interface, a first Intelligent Platform Management Interface (IPMI) original equipment manufacturer (OEM) message from a SMI handler executed under a system management mode (SMM) at a central processing unit (CPU) of the host computer; and
in response to the first IPMI OEM message, perform data transaction between the SP and the host computer by:
in response to the first IPMI OEM message, retrieving specific data stored in the SP, and generating a second IPMI OEM message comprising the specific data; and
sending, via the communication interface, the second IPMI OEM message to the SMI handler executed under the SMM at the CPU of the host computer,

wherein the host computer comprises:
the CPU;
a volatile memory, comprising a system management random access memory (SMRAM) area;
a BIOS chip storing a basic input/output system (BIOS) and the SMI handler; and
a storage device storing an operating system (OS);
wherein the BIOS, when executed at the CPU is configured to
load the SMI handler into the SMRAM area;
load the OS into the volatile memory, and execute the OS at the CPU;

wherein the CPU, when executing the OS, is configured to
receive the first SMI message or a second SMI message; and
in response to receiving the first SMI message or the second SMI message, execute the SMI handler in the SMRAM area at the CPU to enter the SMM; and

wherein the SMI handler, when executed at the CPU, is configured to
generate the first IPMI OEM message, and send the first IPMI OEM message to the SP via the communication interface;
receive, from the SP via the communication interface, the second IPMI OEM message, wherein the second IPMI OEM message indicates whether the SP issued the first SMI message; and
in response to the second IPMI OEM message indicating that the SP issued the first SMI message, perform the data transaction between the SP and the host computer.

2. The system as claimed in claim 1 , wherein the communication interface is a standardized interface under IPMI standard, wherein the standardized interface comprises a keyboard controller style (KCS) interface, a system management interface chip (SMIC) interface, and a block transfer (BT) interface.

3. The system as claimed in claim 1 , wherein the SP is a baseboard management controller (BMC).

4. The system as claimed in claim 1 , wherein the second SMI message is generated by the OS executed at the CPU.

5. The system as claimed in claim 1 , wherein the CPU of the host computer has a SMI pin connected to the SP through a communication link different from the communication interface, wherein the CPU is configured to receive the first SMI message from the SP through the communication link.

6. The system as claimed in claim 1 , wherein the host computer further comprises a platform controller hub (PCH) hardware, wherein the SP is connected to the PCH hardware through a communication link different from the communication interface.

7. The system as claimed in claim 6 , wherein the PCH hardware is configured to
receive the first SMI message through the communication link, and
in response to the first SMI message, generate a hardware SMI and send the hardware SMI to the CPU as the SMI message.

8. The system as claimed in claim 1 , wherein the SMI handler, when executed at the CPU, is configured to perform the data transaction by:
receiving, via the communication interface, the second IPMI OEM message from the SP; and
retrieving the specific data from the second IPMI OEM message.

9. A system, comprising:
a service processor (SP), comprising a processor, a non-volatile memory, and a communication interface, wherein the non-volatile memory stores computer executable code configured to, when executed at the processor,
generate a first system management interrupt (SMI) message, and send the first SMI message to a host computer;
receive, via the communication interface, a first Intelligent Platform Management Interface (IPMI) original equipment manufacturer (OEM) message from a SMI handler executed under a system management mode (SMM) at a central processing unit (CPU) of the host computer; and
in response to the first IPMI OEM message, perform data transaction between the SP and the host computer by:
in response to the first IPMI OEM message, generating a response, and sending, via the communication interface, the response to the BIOS executed under the SMM at the CPU of the host computer, wherein the response comprises a data transaction request; and
receiving, via the communication interface, a data collection to the data transaction request from the SMI handler executed under the SMM at the CPU of the host computer, wherein the data collection comprises specific data requested by the data transaction request,

wherein the host computer comprises:
the CPU;
a volatile memory, comprising a system management random access memory (SMRAM) area;
a BIOS chip storing a basic input/output system (BIOS) and the SMI handler; and
a storage device storing an operating system (OS);
wherein the BIOS, when executed at the CPU is configured to
load the SMI handler into the SMRAM area;
load the OS into the volatile memory, and execute the OS at the CPU;

wherein the CPU, when executing the OS, is configured to
receive the first SMI message or a second SMI message; and
in response to receiving the first SMI message or the second SMI message, execute the SMI handler in the SMRAM area at the CPU to enter the SMM; and

wherein the SMI handler, when executed at the CPU, is configured to
generate the first IPMI OEM message, and send the first IPMI OEM message to the SP via the communication interface;
receive, from the SP via the communication interface, a response to the first IPMI OEM message, wherein the response indicates whether the SP issued the first SMI message; and
in response to the response indicating that the SP issued the first SMI message, perform the data transaction between the SP and the host computer.

10. The system as claimed in claim 9 , wherein the SMI handler, when executed at the CPU, is configured to perform the data transaction by:
receiving, via the communication interface, the response from the SP;
retrieving the data transaction request from the response;
retrieving the specific data based on the data transaction request, and generate the data collection with the specific data; and
sending, via the communication interface, the data collection to the SP.

11. The system as claimed in claim 10 , wherein the response is a second IPMI OEM message, and the data collection is a third IPMI OEM message comprising the specific data.

12. A method of performing data transaction between a service processor (SP) and a host computer, comprising:
generating, by the SP, a first system management interrupt (SMI) message, and sending the first SMI message to the host computer;
loading, at the host computer, a basic input/output system (BIOS) from a BIOS chip of the host computer, and executing the BIOS at the CPU;
loading, by the BIOS executed at the CPU, a SMI handler from the BIOS chip into a system management random access memory (SMRAM) area into a volatile memory of the host computer;
loading, by the BIOS executed at the CPU, the OS into the volatile memory, and execute t

Assignees

• American Megatrends Inc

Inventors

• Maity Sanjoy
• Nallagatla Purandhar
• Doppalapudi Harikrishna
• Bhimanadhuni Ramakoti Reddy
• Thomas Satheesh
• Inbaraj Joseprabu

Classifications

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F13/32 Primary

  using combination of interrupt and burst mode transfer · CPC title