Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes

Patent metadata

Field	Value
Publication number	US-2016011997-A1
Application number	US-201514866262-A
Country	US
Kind code	A1
Filing date	Sep 25, 2015
Priority date	Oct 9, 2009
Publication date	Jan 14, 2016
Grant date	—

Abstract

Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

First claim

1 - 47 . (canceled)

48 . A system, comprising:
one or more processors operable to run a plurality of kernel threads, a different one or ones of the kernel threads being awake and in operation at different times; a memory coupled to the one or more processors, the memory storing a correspondence between an interrupt identifier of a plurality of interrupt identifiers and a given kernel thread of the plurality of kernel threads; and an Input/Output (I/O) device coupled to the one or more processors and the memory, wherein upon occurrence of an event that would cause the I/O device to direct an interrupt to the given kernel thread, the I/O device identifies whether the given kernel thread is awake, the I/O device being operable to bind the given kernel thread to a unique processor of the one or more processors in the system, the unique processor being associated with the interrupt identifier corresponding to the given kernel thread according to an interrupt mapping scheme comprising associations between the one or more processors and one or more of the plurality of interrupt identifiers.

49 . The system of claim 48 , wherein the I/O device is operable to insert the given kernel thread in a thread queue in the unique processor to which the worker kernel thread is bound.

50 . The system of claim 48 , wherein the I/O device is operable to wake up the given kernel thread if it is determined that the given kernel thread is not awake.

51 . (canceled)

52 . The system of claim 48 , wherein if it is determined that the given kernel thread is awake and in operation, the I/O device is operable to raise the interrupt immediately.

53 . The system of claim 48 , wherein if it is determined that the given kernel thread is not awake or in operation, the I/O device is operable to use an interrupt identifier to generate the interrupt.

54 . The system of claim 48 , wherein the I/O device is operable to detect a total number of interrupt identifiers available in the system.

55 . The system of claim 48 , wherein the event that would cause the I/O device to direct the interrupt to the given kernel thread is an I/O completion.

56 . The system of claim 48 , wherein the I/O device is operable to create a kernel thread for handling an interrupt.

57 . The system of claim 49 , wherein the I/O device is operable to assign a priority to the given kernel thread, the priority indicating when the kernel thread is to be serviced in the thread queue.

58 . A method for processing interrupts, the method comprising:
running a plurality of kernel threads in one or more processors, a different one or ones of the kernel threads being awake and in operation at different times; storing a correspondence between an interrupt identifier of a plurality of interrupt identifiers and a given kernel thread of the plurality of kernel threads; and binding the given kernel thread to a unique processor of the one or more processors, the unique processor being associated with the interrupt identifier corresponding to the given kernel thread according to an interrupt mapping scheme comprising associations between the one or more processors and one or more of the plurality of interrupt identifiers.

59 . The method of claim 58 , wherein the method comprises inserting the given kernel thread in a thread queue in the unique processor to which the worker kernel thread is bound.

60 . The method of claim 59 , wherein the method comprises assigning a priority to the given kernel thread, the priority indicating when the kernel thread is to be serviced in the thread queue.

61 . The method of claim 58 , wherein the method comprises:
identifying whether the given kernel thread is awake; and waking up the given kernel thread if it is determined that the given kernel thread is not awake.

62 . The method of claim 58 , wherein the method comprises:
determining that the given kernel thread is awake and in operation; and raising the interrupt immediately.

63 . The method of claim 58 , wherein the method comprises:
determining that the given kernel thread is not awake or in operation; and using an interrupt identifier to generate the interrupt.

64 . The method of claim 58 , wherein the method comprises detecting an occurrence of an event that triggers an interrupt.

65 . The method of claim 64 , wherein the event that triggers an interrupt is an I/O completion.

66 . The method of claim 58 , wherein the method detecting a total number of interrupt identifiers available in the system.

67 . The method of claim 58 , wherein the method comprises creating a kernel thread for handling an interrupt.

68 . A computing apparatus, comprising:
one or more processors operable to run a plurality of kernel threads, a different one or ones of the kernel threads being awake and in operation at different times; a memory coupled to the processors, the memory storing a correspondence between a respective interrupt identifier and a kernel thread of the plurality of kernel threads; and an Input/Output (I/O) device coupled to the processors and the memory, wherein upon occurrence of a triggering event, the I/O device identifies whether the given kernel thread is active, the I/O device being operable to raise the interrupt immediately when the given kernel thread is active, the I/O device being operable to use an interrupt identifier to generate an interrupt and bind the given kernel thread to a processor of the one or more processors when the given kernel thread is not active.

Assignees

• Avago Technologies General Ip

Inventors

• Liu Qiang
• Andrews Allen Russell
• Baldwin David Bradley

Classifications

• G06F9/5033

  considering data affinity · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F3/0632

  by initialisation or re-initialisation of storage systems · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title