I2C controller register, control, command and R/W buffer queue logic

Patent metadata

Field	Value
Publication number	US-9336167-B2
Application number	US-201213720442-A
Country	US
Kind code	B2
Filing date	Dec 19, 2012
Priority date	Dec 13, 2012
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

First claim

What is claimed is:

1. A process of transferring data on an I2C bus comprising:
receiving I2C bus slave addresses from a host processor in a slave address register in an I2C bus controller;
accumulating the I2C bus slave addresses from the slave address register in a command register in the I2C bus controller;
receiving from the host processor I2C bus slave data in data FIFO registers in the I2C bus controller;
receiving from the host processor a start bit in a control register in the I2C bus controller;
sending the I2C bus slave data from the data FIFO registers to the I2C bus slave addresses over an I2C bus in response to receiving the start bit; and
sending an interrupt signal to the host processor only after sending all of the I2C bus slave data to all of the I2C bus slave addresses.

2. The process of claim 1 in which accumulating includes accumulating up to five I2C bus slave addresses in the command register.

3. The process of claim 1 in which the receiving I2C bus slave addresses in a slave address register is prohibited after the receiving a start bit in the command register.

4. The process of claim 1 in which the sending I2C bus slave data over an I2C bus includes sending the I2C bus slave data from the data FIFO registers through I2C logic to the I2C bus.

5. The process of claim 1 including receiving an ACK/NAK signal from a slave device after sending first I2C bus slave data to a first address over the I2C bus in response to receiving the start bit, refraining from sending an interrupt signal after receiving the ACK/NAK signal, and sending second I2C bus slave data to a second address over the I2C bus.

Assignees

• Texas Instruments Inc

Inventors

• Danis Frederic
• Badi Eric Louis Pierre

Classifications

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F13/32 Primary

  using combination of interrupt and burst mode transfer · CPC title

• G06F13/1642

  with request queuing · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title