Virtual container storage interface controller
US-12175078-B2 · Dec 24, 2024 · US
US9262197B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9262197-B2 |
| Application number | US-201414333343-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 16, 2014 |
| Priority date | Jul 16, 2014 |
| Publication date | Feb 16, 2016 |
| Grant date | Feb 16, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).
Opening claim text (preview).
What is claimed is: 1. A method for accelerating data transfer operations, the method comprising: prior to booting a hypervisor on a processor subsystem having a root complex, configuring a first Peripheral Component Interconnect Express (PCI-E) endpoint and a second PCI-E endpoint associated with an accelerator device, wherein the accelerator device is a physical PCI-E device exclusively accessible to the processor subsystem; booting the hypervisor using the processor subsystem; loading a storage virtual appliance (SVA) as a virtual machine on the hypervisor, wherein the hypervisor assigns the second PCI-E endpoint for exclusive access by the SVA using a second root port of the root complex; activating the first PCI-E endpoint by the SVA using a first root port of the root complex via the second PCI-E endpoint; responsive to activating the first PCI-E endpoint, loading a hypervisor device driver for the first PCI-E endpoint, wherein the first PCI-E endpoint appears to the hypervisor as a logical hardware adapter accessible via the hypervisor device driver; and initiating, by the SVA, a data transfer operation between the first PCI-E endpoint and the second PCI-E endpoint. 2. The method of claim 1 , wherein the data transfer operation is between a first virtual machine and a second virtual machine executing on the hypervisor. 3. The method of claim 2 , wherein the first PCI-E endpoint is associated with a first address space for the first virtual machine and the second PCI-E endpoint is associated with a second address space for the second virtual machine, wherein the accelerator device performs address translation transactions between the first address space and a physical memory address space and between the second address space and the physical memory address space. 4. The method of claim 3 , wherein the accelerator device performs address translation caching for the address translation transactions, wherein the address translation caching is performed before the data transfer operation is initiated. 5. The method of claim 1 , wherein the data transfer operation includes a direct memory access (DMA) operation performed by the accelerator device, and wherein initiating the data transfer operation includes: causing, by the SVA, DMA parameters for the DMA operation to be sent the accelerator device. 6. The method of claim 1 , wherein the data transfer operation includes a programmed input/output (PIO) operation performed by the accelerator device. 7. The method of claim 1 , further comprising, by the SVA via the second PCI-E endpoint: when the data transfer operation is in progress, terminating the data transfer operation; deactivating the first PCI-E endpoint; programming, on the accelerator device, a first personality profile for the first PCI-E endpoint and a second personality profile for the second PCI-E endpoint, wherein a personality profile includes configuration information for a PCI-E endpoint; restarting the second PCI-E endpoint; and responsive to restarting the second PCI-E endpoint, restarting the first PCI-E endpoint. 8. The method of claim 1 , wherein the data transfer operation includes data processing operations performed by the accelerator device, wherein the data processing operations are selected from: encryption; compression; checksum; and malicious code detection. 9. The method of claim 1 , wherein the SVA uses the second PCI-E endpoint to access a private device on the accelerator device, the private device selected from: a memory device; a network interface adapter; a storage adapter; and a storage device. 10. The method of claim 2 , wherein the SVA programs the accelerator device to generate interrupts associated with the data transfer operation. 11. An information handling system, comprising: an accelerator device that is a physical Peripheral Component Interconnect Express (PCI-E) device; a processor subsystem having access to a memory subsystem and having exclusive access to the accelerator device, wherein the memory subsystem stores instructions executable by the processor subsystem for accelerating data transfer operations on a hypervisor using the accelerator device, the instructions, when executed by the processor subsystem, cause the processor subsystem to: prior to executing instructions to boot the hypervisor, configure a first PCI-E endpoint and a second PCI-E endpoint associated with the accelerator device; boot the hypervisor using the processor subsystem; load a storage virtual appliance (SVA) as a virtual machine on the hypervisor, wherein the hypervisor assigns the second PCI-E endpoint for exclusive access by the SVA; activate the first PCI-E endpoint by the SVA via the second PCI-E endpoint; responsive to the instructions to activate the first PCI-E endpoint, load a hypervisor device driver for the first PCI-E endpoint, wherein the first PCI-E endpoint appears to the hypervisor as a logical hardware adapter accessible via the hypervisor device driver; and initiate, by the SVA, a data transfer operation between the first PCI-E endpoint and the second PCI-E endpoint. 12. The information handling system of claim 11 , wherein the data transfer operation is between a first virtual machine and a second virtual machine executing on the hypervisor. 13. The information handling system of claim 12 , wherein the first PCI-E endpoint is associated with a first address space for the first virtual machine and the second PCI-E endpoint is associated with a second address space for the second virtual machine, wherein the accelerator device performs address translation transactions between the first address space and a physical memory address space and between the second address space and the physical memory address space. 14. The information handling system of claim 13 , wherein the accelerator device performs address translation caching for the address translation transactions, wherein the address translation caching is performed before the data transfer operation is initiated. 15. The information handling system of claim 11 , wherein the data transfer operation includes a direct memory access (DMA) operation performed by the accelerator device, and wherein the instructions to initiate the data transfer operation include instructions to: cause, by the SVA, DMA parameters for the DMA operation to be sent the accelerator device. 16. The information handling system of claim 11 , wherein the data transfer operation includes a programmed input/output (PIO) operation performed by the accelerator device. 17. The information handling system of claim 11 , further comprising instructions executed by the SVA via the second PCI-E endpoint to: when the data transfer operation is in progress, terminate the data transfer operation; deactivate the first PCI-E endpoint; program, on the accelerator device, a first personality profile for the first PCI-E endpoint and a second personality profile for the second PCI-E endpoint, wherein a personality profile includes configuration information for a PCI-E endpoint; restart the second PCI-E endpoint; and responsive to the instructions to restart the second PCI-E endpoint, restart the first PCI-E endpoint. 18. The information handling system of claim 11 , wherein the data transfer operation includes data processing operations performed by the accelerator device, wherein the data processing operations are selected from: encryption; compression; checksum; and malicious code detection. 19. The information handling system of claim
I/O management, e.g. providing access to device drivers or storage · CPC title
with dedicated cache, e.g. instruction or stack · CPC title
Hypervisor-specific management and integration aspects · CPC title
using combination of interrupt and burst mode transfer · CPC title
resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.