Memory system and operating method thereof
US-2019361778-A1 · Nov 28, 2019 · US
Error in check bits
Error in check bits · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F11/102 |
| Official title | {Error in check bits} |
| Display label | Error in check bits |
| Total patents | 334 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 8 |
| 2016 | 9 |
| 2017 | 13 |
| 2018 | 14 |
| 2019 | 21 |
| 2020 | 55 |
| 2021 | 50 |
| 2022 | 52 |
| 2023 | 30 |
| 2024 | 33 |
| 2025 | 40 |
| 2026 | 9 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Memory device with soft-decision decoding and methods of reading and forming thereof
US-2019361769-A1 · Nov 28, 2019 · US
Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same
US-10476529-B2 · Nov 12, 2019 · US
Transaction metadata
US-2019324843-A1 · Oct 24, 2019 · US
Error correction using hierarchical decoders
US-2019324848-A1 · Oct 24, 2019 · US
Method and device for programming non-volatile memory
US-10445173-B2 · Oct 15, 2019 · US
Memory system and operating method thereof
US-10379955-B2 · Aug 13, 2019 · US
Storage system and method of managing volumes thereof based on received correlation information of the volumes
US-10353641-B2 · Jul 16, 2019 · US
Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system
US-2019199376-A1 · Jun 27, 2019 · US
Bitwise sparing in a memory system
US-10261856-B2 · Apr 16, 2019 · US
Inner and outer code generator for volatile memory
US-2019108147-A1 · Apr 11, 2019 · US
Systems and methods for facilitating truly random bit generation
US-2019095269-A1 · Mar 28, 2019 · US
Memory device, memory system including the same, and operating method of memory system
US-2019012230-A1 · Jan 10, 2019 · US
Memory system and method for operating semiconductor memory device
US-2019012227-A1 · Jan 10, 2019 · US
Memory device, memory system including the same, and operating method of memory system
US-2019012231-A1 · Jan 10, 2019 · US
Modifiable stripe length in flash memory devices
US-10169141-B2 · Jan 1, 2019 · US
Method and device for programming non-volatile memory
US-2018373584-A1 · Dec 27, 2018 · US
Methods of correcting data errors and semiconductor devices used therein
US-10162703-B2 · Dec 25, 2018 · US
Memory system and operating method thereof
US-2018285197-A1 · Oct 4, 2018 · US
Intelligent refresh of 3d nand
US-2018203758-A1 · Jul 19, 2018 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F11/102?
- CPC G06F11/102 is the Cooperative Patent Classification code for “Error in check bits.”
- How many patents are filed under CPC G06F11/102 (Error in check bits)?
- Our database includes 334 publications tagged with this CPC code.
- Is patent activity under CPC G06F11/102 growing?
- Publication counts under this code: 33 in 2024 vs 40 in 2025 (latest complete years).