Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Patent metadata

Field	Value
Publication number	US-10476529-B2
Application number	US-201715789653-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Dec 2, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

First claim

What is claimed is:

1. An error detection code generation circuit of a semiconductor device, the error detection code generation circuit comprising:
a first cyclic redundancy check (CRC) engine configured to generate first error detection code bits using a first generation matrix, based on a plurality of first unit data and first data bus inversion (DBI) bits, wherein each of the first DBI bits indicates whether a corresponding bit of the first unit data is inverted;
a second CRC engine configured to generate second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, wherein each of the second DBI bits indicates whether a corresponding bit of the second unit data is inverted;
a multiplexer configured to select one of a most significant bit of the second error detection code bits and an inverted version of the most significant bit of the second error detection code bits in response to a mode signal indicating a code rate mode; and
an output selection engine configured to generate final error detection code bits by merging the first error detection code bits, and the second error detection code bits and the selected one of the second error detection code bits in response to the mode signal,
wherein the first generation matrix is the same as the second generation matrix.

2. The error detection code generation circuit of claim 1 , wherein when the mode signal designates a first code rate mode,
the first CRC engine is configured to generate the first error detection code bits by using the first generation matrix,
the second CRC engine is configured to generate the second error detection code bits by using the second generation matrix, and
the output selection engine is configured to provide the first error detection code bits as upper bits of the final error detection code bits and to provide the second error detection code bits as lower bits of the final error detection code bits.

3. The error detection code generation circuit of claim 1 , wherein when the mode signal designates a second code rate mode,
the output selection engine is configured to output the final error detection code bits by merging corresponding bits of the first error detection code bits and the second error detection code bits, and
the second code rate mode includes a first sub code rate mode, and a second sub code rate mode.

4. The error detection code generation circuit of claim 3 , wherein when the mode signal designates the first sub code rate mode,
the first CRC engine is configured to generate the first error detection code bits by using the first generation matrix,
the second CRC engine is configured to generate the second error detection code bits by using a second modified matrix, and
the second modified matrix is generated by inverting matrix elements of rows of the second generation matrix, wherein the inverted matrix elements are associated with the most significant bit of the second error detection code bits.

5. The error detection code generation circuit of claim 3 , wherein when the mode signal designates the second sub code rate mode,
the first CRC engine is configured to generate the first error detection code bits by using the first generation matrix,
the second CRC engine is configured to generate the second error detection code bits by using a second modified matrix, and
the second modified matrix is generated by inverting all or some of matrix elements of a portion of rows of the second generation matrix.

6. The error detection code generation circuit of claim 3 , wherein when the mode signal designates the second sub code rate mode,
the first CRC engine is configured to generate the first error detection code bits by using a first modified matrix,
the second CRC engine is configured to generate the second error detection code bits by using a second modified matrix,
the first modified matrix is generated by inverting matrix elements of rows of the first generation matrix, wherein the inverted matrix elements of the first generation matrix are associated with a most significant bit of the first error detection code bits, and
the second modified matrix is generated by inverting matrix elements of rows of the second generation matrix, wherein the inverted matrix elements of the second generation matrix are associated with the most significant bit of the second error detection code bits.

7. A memory controller, comprising:
an error detection code generation circuit configured to generate first error detection code bits based on a plurality of first unit data and first data bus inversion (DBI) bits, wherein each of the first DBI bits indicates whether a corresponding bit of the first unit data is inverted, to generate second error detection code bits based on a plurality second unit data and second DBI bits, wherein each of the second DBI bits indicates whether a corresponding bit of the second unit data is inverted, to select one of a most significant bit of the second error detection code bits and an inverted version of the most significant bit of the second error detection code bits in response to a mode signal, to output the selected error detection code bit and to generate final error detection code bits by merging the first error detection code bits, the second error detection code bits and the selected error detection code bit, wherein the mode signal indicates a code rate mode and the first unit data and the second unit data are included in a main data; and
an error detector configured to detect errors of the main data which is to be transmitted to a semiconductor memory device, based on return final error detection code bits and the final error detection code bits, wherein the semiconductor memory device is configured to receive the main data, the first DBI bits and the second DBI bits to generate the return final error detection code bits,
wherein the error detection code generation circuit is configured to generate the first error detection code bits and the second error detection code bits by using a same generation matrix.

8. The memory controller of claim 7 , wherein the error detector comprises:
a first buffer to store the final error detection code bits;
a second buffer to store the return final error detection code bits;
a comparator connected to the first buffer and the second buffer, the comparator configured to compare corresponding bits of the final error detection code bits and the return final error detection code bits and to generate syndrome data which indicates a match between the corresponding bits of the final error detection code bits and the return final error detection code bits; and
a detector configured to generate a detection signal which indicates whether the main data includes the errors, in response to the syndrome data.

9. The memory controller of claim 7 , wherein the error detection code generation circuit comprises:
a first cyclic redundancy check (CRC) engine configured to generate the first error detection code bits using a first generation matrix, based on the first unit data and the first DBI bits in response to the mode signal;
a second CRC engine configured to generate the second error detection code bits using a second generation matrix, based on the second unit data and second DBI bits, in response to the mode signal; and
an output selection engine configured to generate the final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal, wherein the first generation matrix is the same as the second generation matrix.

10. The memory controller of claim 9 , wherein a number of the final error detection

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Ryu Ye-Sin
• Kim Young-Sik
• Doo Su-Yeon

Classifications

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/102 Primary

  Error in check bits · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title