Methods of correcting data errors and semiconductor devices used therein

Patent metadata

Field	Value
Publication number	US-10162703-B2
Application number	US-201615373045-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Jun 23, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub-matrix and a second sub-matrix. The first sub-matrix includes column vectors having an odd weight. The second sub-matrix includes an up matrix and a down matrix. Each of the up matrix and the down matrix includes column vectors having an odd weight.

First claim

What is claimed is:

1. A semiconductor device comprising:
a parity generation circuit configured to generate a parity signal from an input data signal using a hamming code;
a data storage circuit configured to store the input data signal and the parity signal during a write operation and configured to generate an output data signal and an output parity signal during a read operation; and
a syndrome generation circuit configured to generate a syndrome signal for correcting errors of the output data signal from the output data signal and the output parity signal using the hamming code,
wherein the hamming code is applied in the form of an error check matrix,
wherein the error check matrix includes a first sub-matrix and a second sub-matrix,
wherein the first sub-matrix includes column vectors having an odd weight,
wherein the second sub-matrix includes an up matrix and a down matrix,
wherein each of the up matrix and the down matrix includes column vectors having an odd weight, and
wherein the syndrome generation circuit further comprises:
a plurality of internal syndrome generation circuits;
each of the plurality of internal syndrome generation circuits comprising a combination of logic gates to receive multiple output data signals and one output parity signal to output the syndrome signal,

wherein the syndrome signal is configured to prevent an erroneous correction of a data bit of the output data signal when at least two data bit errors are included in the output data signal.

2. The semiconductor device of claim 1 , wherein a number of bits included in each of the column vectors of the first sub-matrix is equal to a number of bits included in the parity signal.

3. The semiconductor device of claim 1 , wherein a sum of a number of bits included in each of the column vectors of the up matrix and a number of bits included in each of the column vectors of the down matrix is equal to a number of bits included in the parity signal.

4. The semiconductor device of claim 1 , wherein each of the column vectors of the first sub-matrix includes an odd number of three or more bits, where the bits have a value of ‘1’.

5. The semiconductor device of claim 1 ,
wherein each of the column vectors of the up matrix includes an odd number of one or more bits having a value of ‘1’; and
wherein each of the column vectors of the down matrix includes an odd number of one or more bits having a value of ‘1’.

6. A semiconductor device comprising:
a parity generation circuit configured to generate a parity signal from an input data signal using a hamming code;
a data storage circuit configured to store the input data signal and the parity signal during a write operation and configured to generate an output data signal and an output parity signal during a read operation; and
a syndrome generation circuit configured to generate a syndrome signal for correcting errors of the output data signal from the output data signal and the output parity signal using the hamming code,
wherein the hamming code is applied in the form of an error check matrix,
wherein the error check matrix includes a first sub-matrix and a second sub-matrix,
wherein the first sub-matrix includes column vectors having an odd weight,
wherein the second sub-matrix includes a first up matrix, a first down matrix, a second up matrix and a second down matrix,
wherein the first down matrix includes column vectors having an even weight,
wherein each of the first up matrix, the second up matrix and the second down matrix includes column vectors having an odd weight, and
wherein the syndrome generation circuit further comprises:
a plurality of internal syndrome generation circuits;
each of the plurality of internal syndrome generation circuits comprising a combination of logic gates to receive multiple output data signals and one output parity signal to output the syndrome signal,

wherein the syndrome signal is configured to prevent an erroneous correction of a data bit of the output data signal when at least two data bit errors are included in the output data signal.

7. The semiconductor device of claim 6 , wherein a sum of a number of bits included in each of the column vectors of the first up matrix and a number of bits included in each of the column vectors of the first down matrix equals a number of bits included in the parity signal.

8. The semiconductor device of claim 6 ,
wherein each of the column vectors of the first up matrix includes one or more odd number of bits having a value of ‘1’; and
wherein each of the column vectors of the first down matrix includes an even number of bits having a value of ‘1’.

9. The semiconductor device of claim 6 , wherein a sum of a number of bits included in each of the column vectors of the second up matrix and a number of bits included in each of the column vectors of the second down matrix is equal to a number of bits included in the parity signal.

10. The semiconductor device of claim 6 ,
wherein each of the column vectors of the second up matrix includes one or more odd number of bits having a value of ‘1’; and
wherein each of the column vectors of the second down matrix includes one or more odd number of bits having a value of ‘1’.

11. A semiconductor device comprising:
a parity generation circuit configured to generate a parity signal from an input data signal using a hamming code;
a data storage circuit configured to store the input data signal and the parity signal during a write operation and configured to generate an output data signal and an output parity signal during a read operation; and
a syndrome generation circuit configured to generate a syndrome signal for correcting errors of the output data signal from the output data signal and the output parity signal using the hamming code,
wherein the hamming code is applied in the form of an error check matrix,
wherein the error check matrix includes a first sub-matrix and a second sub-matrix,
wherein the first sub-matrix includes column vectors having an odd weight,
wherein the second sub-matrix includes a first up matrix, a first down matrix, a second up matrix and a second down matrix,
wherein the first up matrix includes column vectors having an even weight,
wherein each of the first down matrix, the second up matrix and the second down matrix includes column vectors having an odd weight, and
wherein the syndrome generation circuit further comprises:
a plurality of internal syndrome generation circuits;
each of the plurality of internal syndrome generation circuits comprising a combination of logic gates to receive multiple output data signals and one output parity signal to output the syndrome signal,

wherein the syndrome signal is configured to prevent an erroneous correction of a data bit of the output data signal when at least two data bit errors are included in the output data signal.

12. The semiconductor device of claim 11 ,
wherein a sum of a number of bits included in each of the column vectors of the first up matrix and a number of bits included in each of the column vectors of the first down matrix is equal to a number of bits included in the parity signal; and
wherein a sum of a number of bits included in each of the column vectors of the second up matrix and a number of bits included in each of the column vectors of the second down matrix is equal to the number of bits included in the parity signal.

13. The semiconductor device of claim 11 ,
wherein each of the column vectors of the first up matrix includes an even number of bits having a value of ‘1’;
wherein each of the column vectors of the first down matrix includes one or more odd nu

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang Hyun

Classifications

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/064

  Management of blocks · CPC title