Methods of operating nonvolatile memory devices that support efficient error detection
US-9183924-B2 · Nov 10, 2015 · US
US10445173B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10445173-B2 |
| Application number | US-201715632460-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 26, 2017 |
| Priority date | Jun 26, 2017 |
| Publication date | Oct 15, 2019 |
| Grant date | Oct 15, 2019 |
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A method for programming a non-volatile memory in a programming operation is provided. The non-volatile memory has a number of cells and each of part of the cells stores data having at least 2 bits at least corresponding to a first page and a second page. The first programming-verifying operation including programming the first page and verifying whether the first page is successfully programmed is performed. When a first original fail-bit number for the first page is more than a predetermined fail-bit value, a second programming-verifying operation to the first page is performed to obtain a first over-counting fail-bit number for the first page and reduce the first original fail-bit number by the first over-counting fail-bit number. When the reduced first original fail-bit number is not more than the predetermined fail-bit value, the first page is set as successfully programmed.
Opening claim text (preview).
What is claimed is: 1. A method for programming a non-volatile memory in a programming operation, wherein each of part of a plurality of cells of the non-volatile memory stores data having at least 2 bits at least corresponding to a first page and a second page, the method comprising: performing a first programming-verifying operation to the cells of the first page, the first programming-verifying operation comprising programming the cells of the first page and verifying whether the cells of the first page is successfully programmed; determining whether a first original fail-bit number for the cells of the first page is more than a predetermined value, if yes, setting the first page as failed; performing a second programming-verifying operation to the cells of the first page when the first page is set as failed, the second programming-verifying operation comprising obtaining a first over-counting fail-bit number for the first page and reducing the first original fail-bit number by the first over-counting fail-bit number; and determining whether the reduced first original fail-bit number is more than the predetermined value, if not, setting the first page as successfully programmed. 2. The method according to claim 1 , wherein in the step of performing a first programming-verifying operation, at least one programming pulse is provided for programming the cells of the first page, and at least one first program-verify pulse is provided for verifying whether the cells of the first page is successfully programmed. 3. The method according to claim 2 , further comprising: providing a retry-out pulse when a number of the provided at least one programming pulse is equal to a limit. 4. The method according to claim 3 , wherein the second programming-verifying operation is performed after providing the retry-out pulse. 5. The method according to claim 1 , wherein each of the cells has at least a first state, a second state, a third state, and a fourth state, and the first original fail-bit number is the sum of a third state fail-bit number and a fourth state fail-bit number, and the first over-counting fail-bit number is a fourth state to third state fail-bit number. 6. The method according to claim 1 , further comprising: determining whether a second original fail-bit number for the cells of the second page is more than the predetermined value, if yes, setting the second page as failed; performing the second programming-verifying operation to the cells of the second page when the second page is set as failed, the second programming-verifying operation further comprising obtaining a second over-counting fail-bit number for the second page and reducing the second original fail-bit number by the second over-counting fail-bit number; and determining whether the reduced second original fail-bit number is more than the predetermined value, if not, setting the second page as successfully programmed. 7. The method according to claim 6 , wherein each of the cells has at least a first state, a second state, a third state, and a fourth state, and the second original fail-bit number is the sum of a second state fail-bit number, a third state fail-bit number, and a fourth state fail-bit number, and the second over-counting fail-bit number is the sum of a third state to second state fail-bit number and a fourth state to first state fail-bit number. 8. The method according to claim 1 , wherein the first page is set as failed by enabling a program-fail-reference signal, and the first page is set as successfully programmed by disabling the program-fail-reference signal. 9. A method for programming a non-volatile memory in a programming operation, wherein the non-volatile memory has a plurality of multi-level cells, each of part of the multi-level cells stores data having at least 2 bits at least corresponding to a first page and a second page, the method comprising: obtaining a first original fail-bit number and a first over-counting fail-bit number for the first page; reducing the first original fail-bit number by the first over-counting fail-bit number; and determining whether the reduced first original fail-bit number is more than a predetermined value, if not, setting the first page as successfully programmed. 10. The method according to claim 9 , wherein the step of obtaining the first over-counting fail-bit number comprises providing at least one first program-verify pulse to obtain the first over-counting fail-bit number for the first page. 11. The method according to claim 9 , wherein each of the cells has at least a first state, a second state, a third state, and a fourth state, and the first original fail-bit number is the sum of a third state fail-bit number and a fourth state fail-bit number, and the first over-counting fail-bit number is a fourth state to third state fail-bit number. 12. The method according to claim 9 , further comprising: obtaining a second original fail-bit number and a second over-counting fail-bit number for the second page; reducing the second original fail-bit number by the second over-counting fail-bit number; and determining whether the reduced second original fail-bit number is more than the predetermined value, if not, setting the second page as successfully programmed. 13. The method according to claim 12 , wherein each of the cells has at least a first state, a second state, a third state, and a fourth state, and the second original fail-bit number is the sum of a second state fail-bit number, a third state fail-bit number, and a fourth state fail-bit number, and the second over-counting fail-bit number is the sum of a third state to second state fail-bit number and a fourth state to first state fail-bit number. 14. The method according to claim 12 , wherein the step of obtaining the second over-counting fail-bit number comprises providing at least one second program-verify pulse to obtain the second over-counting fail-bit number for the second page.
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