Modifiable stripe length in flash memory devices

Patent metadata

Field	Value
Publication number	US-10169141-B2
Application number	US-201715473237-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Aug 11, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A memory device including a memory having a plurality of memory cells for storing data. The memory device includes a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes. Each individual stripe of the plurality of stripes includes a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells. Stripe lengths (number of data groups) for individual stripes are determined by the controller based on detecting a condition associated with one or more data groups of the plurality of data groups. At least one data group of the plurality of data groups for each of the individual stripes includes parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.

First claim

What is claimed is:

1. A memory device comprising:
a memory comprising a plurality of memory cells for storing data; and
a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes, wherein each individual stripe of the plurality of stripes comprises:
a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells, wherein:
a stripe length for the individual stripe is determined by the controller based on detecting a condition associated with one or more data groups of the plurality of data groups, and
the stripe length for the individual stripe is a number of the plurality of data groups included in the individual stripe; and

at least one data group of the plurality of data groups for each of the individual stripes comprising parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.

2. The memory device of claim 1 , wherein the controller is further configured to:
determine a change in the condition; and
modify the stripe length for the individual stripe based on the change in the condition.

3. The memory device of claim 1 , wherein a first stripe of the plurality of stripes has a first stripe length and a second stripe of the plurality of stripes has a second stripe length wherein the first stripe length and the second stripe length are different.

4. The memory device of claim 1 , wherein the condition is a first condition and wherein the memory device is further configured to determine the stripe length for the individual stripe based on a second condition.

5. The memory device of claim 1 , wherein the condition is a first condition and wherein the memory device is further configured to modify the stripe length for the individual stripe based on a second condition.

6. The memory device of claim 1 , wherein the condition is a bit error rate (BER) for the one or more data groups of the individual stripe.

7. The memory device of claim 6 , wherein the stripe length for the individual stripe is determined such that the BER for the one or more data groups of the individual group is less than a threshold.

8. The memory device of claim 6 , wherein a plurality of BERs is determined comprising the BER for the one or more data groups of each of the plurality of stripes, and wherein the stripe length for each of the plurality of stripes is determined such that each of the plurality of BERs are within a threshold distance of each other.

9. The memory device of claim 6 , wherein the controller is further configured to:
determine the BER for the one or more data groups of the individual stripe.

10. The memory device of claim 1 , wherein the condition is a placement of the memory cells associated with the one or more data groups of the individual stripe within the memory.

11. The memory device of claim 1 , wherein the condition is a number of program erase cycles (PEC) for the one or more data groups of the individual stripe.

12. A method for storing data in a memory comprising a plurality of memory cells, the method comprising:
organizing the data as a plurality of stripes, wherein each individual stripe of the plurality of stripes comprises a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells;
detecting a condition associated with one or more data groups of the plurality of data groups; and
determining a stripe length for the individual stripe based on detecting the condition, wherein the stripe length is a number of the plurality of data groups included in the individual stripe;
wherein at least one data group of the plurality of data groups for each of the individual stripes comprises parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.

13. The method of claim 12 , further comprising:
determining a change in the condition; and
modifying the stripe length for the individual stripe based on the change in the condition.

14. The method of claim 12 , wherein a first stripe of the plurality of stripes has a first stripe length and a second stripe of the plurality of stripes has a second stripe length wherein the first stripe length and the second stripe length are different.

15. The method of claim 12 , wherein the condition is a first condition and wherein the method further comprises:
detecting a second condition associated with the one or more data groups of the plurality of data groups; and
modifying the stripe length for the individual stripe based on detecting the second condition.

16. The method of claim 12 , wherein the condition is a bit error rate (BER) for the one or more data groups of the individual stripe.

17. The method of claim 16 , wherein the stripe length for the individual stripe is determined such that the BER for the one or more data groups of the individual group is less than a threshold.

18. A controller communicatively coupled to a memory comprising a plurality of memory cells for storing data, the controller configured to perform operations comprising:
organizing the data as a plurality of stripes, wherein each individual stripe of the plurality of stripes comprises a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells;
detecting a condition associated with one or more data groups of the plurality of data groups; and
determining a stripe length for the individual stripe based on detecting the condition, wherein the stripe length is a number of the plurality of data groups included in the individual stripe;
wherein at least one data group of the plurality of data groups for each of the individual stripes comprises parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.

19. The controller of claim 18 , the operations further comprising:
determining a change in the condition; and
modifying the stripe length for the individual stripe based on the change in the condition.

20. The controller of claim 18 , wherein the condition is a bit error rate (BER) for the one or more data groups of the individual stripe.

Assignees

• Sk Hynix Inc

Inventors

• Zhang Fan
• Xiong Chenrong
• Cai Yu
• Bhatia Aman
• Kim Hyungseok
• Lee June

Classifications

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F11/102

  Error in check bits · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title