On-going reliability monitoring of integrated circuit chips in the field

Patent metadata

Field	Value
Publication number	US-9310426-B2
Application number	US-201213626040-A
Country	US
Kind code	B2
Filing date	Sep 25, 2012
Priority date	Sep 25, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.

First claim

What is claimed is:

1. An integrated circuit chip comprising:
a functional block comprising a first memory array comprising first bitlines;
a test block comprising a second memory array comprising second bitlines, the first memory array and the second memory array being a same type memory array; and
an embedded processor selectively alternating operation of said test block between a stress mode and a test mode during functioning of said integrated circuit chip within a product,
said embedded processor performing said selectively alternating of said operation of said test block between said stress mode and said test mode when said integrated circuit chip is powered-on within said product,
said first bitlines being pre-charged at a nominal operating voltage during said operation of said test block in said stress mode and said test mode,
said embedded processor causing said second bitlines to be pre-charged at a higher voltage level than said nominal operating voltage during said stress mode,
said embedded processor causing said second bitlines to be pre-charged at a same voltage level as said nominal operating voltage and to be subjected to testing during said test mode, and
said embedded processor further being remote access service (RAS) enabled so as to allow results of said testing to be reported out during said functioning of said integrated circuit chip.

2. The integrated circuit chip of claim 1 , said functional block and said test block each comprising a static random access memory (SRAM) array.

3. The integrated circuit chip of claim 1 , said test block comprising a lesser number of devices than said functional block.

4. The integrated circuit chip of claim 1 , said testing comprising:
performing pass/fail testing to determine a pass/fail status of said test block; and
performing parametric testing to detect and measure any shift in a parameter associated with said test block.

5. The integrated circuit chip of claim 1 , said embedded processor further performing said selectively alternating of said operation of said test block between said stress mode and said test mode such that said testing is performed at regular predetermined intervals.

6. The integrated circuit chip of claim 1 , further comprising a monitor tracking environmental conditions associated with said test block.

7. An integrated circuit chip comprising:
a functional block comprising a first memory array comprising first bitlines;
a test block comprising a second memory array comprising second bitlines, the first memory array and the second memory array being a same type memory array;
a monitor tracking environmental conditions associated with said test block; and
an embedded processor in communication with said test block and said monitor,
said embedded processor selectively alternating operation of said test block between a stress mode and a test mode during functioning of said integrated circuit chip within a product,
said embedded processor performing said selectively alternating of said operation of said test block between said stress mode and said test mode when said integrated circuit chip is powered-on within said product,
said first bitlines being pre-charged at a nominal operating voltage during said operation of said test block in said stress mode and said test mode,
said embedded processor causing said second bit lines to be pre-charged at a higher voltage level than said nominal operating voltage during said stress mode,
said embedded processor causing said second bitlines to be pre-charged at a same voltage level as said nominal operating voltage and to be subjected to testing during said test mode, and
said embedded processor further being remote access service (RAS) enabled so as to allow results of said testing and said tracking be reported out during said functioning of said integrated circuit chip.

8. The integrated circuit chip of claim 7 , said functional block and said test block each comprising a static random access memory (SRAM) array.

9. The integrated circuit chip of claim 7 , said test block comprising a lesser number of devices than said functional block.

10. The integrated circuit chip of claim 7 , said testing comprising:
performing pass/fail testing to determine a pass/fail status of said test block; and
performing parametric testing to detect and measure any shift in a parameter associated with said test block.

11. The integrated circuit chip of claim 7 , said embedded processor further performing said selectively alternating of said operation of said test block between said stress mode and said test mode such that said testing is performed at regular predetermined intervals.

12. The integrated circuit chip of claim 11 , said regular predetermined intervals being any one of daily, weekly and monthly.

13. An integrated circuit chip comprising:
a functional block comprising a first static random access memory (SRAM) array comprising first static random access memory (SRAM) cells and first bitlines;
a test block comprising a second static random access memory (SRAM) array comprising second static random access memory (SRAM) cells and second bitlines; and
an embedded processor selectively alternating operation of said test block between a stress mode and a test mode during functioning of said integrated circuit chip within a product,
said first bitlines being pre-charged to a nominal operating voltage during memory operations are performed by said functional block and regardless of whether said operation of said test block is in said stress mode or said test mode,
said embedded processor performing said selectively alternating of said operation of said test block between said stress mode and said test mode when said integrated circuit chip is powered-on within said product,
said embedded processor causing said first static random access memory (SRAM) cells and said second static random access memory (SRAM) array to be exercised at a same frequency during said stress mode,
said embedded processor causing said second bitlines to be pre-charged at a higher voltage level than said nominal operating voltage of said first bitlines during said stress mode,
said embedded processor causing said second bitlines to be pre-charged to a same voltage level as said nominal operating voltage of said first bitlines and to be subjected to testing during said test mode; and
said embedded processor further being remote access service (RAS) enabled so as to allow results of said testing to be reported out during said functioning of said integrated circuit chip.

14. The integrated circuit chip of claim 13 , said first static random access memory (SRAM) array having a first number of said first static random access memory (SRAM) cells, said second static random access memory (SRAM) array having a second number of said second static random access memory (SRAM) cells, said first number being greater than said second number.

15. The integrated circuit chip of claim 13 , said testing comprising:
performing pass/fail testing to determine a pass/fail status of said test block; and
performing parametric testing to detect and measure any shift in a parameter associated with said test block.

16. The integrated circuit chip of claim 13 , said embedded processor selectively alternating said operation of said test block between said stress mode and said test mode such that said testing is performed at regular predetermined intervals.

17. The integrated circuit chip of claim 13 , further comprising a monitor tracking environmental conditions associated with said test bloc

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Anemikos Theodoros E
• Dewey Douglas S
• Nsame Pascal A
• Polson Anthony D

Classifications

• G01R31/2872

  related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation · CPC title

• G11C29/06

  Acceleration testing · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C2029/0401

  in embedded memories · CPC title

• G01R31/2856 Primary

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title