Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof

Patent metadata

Field	Value
Publication number	US-9997593-B2
Application number	US-201715646084-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Aug 9, 2014
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.

First claim

What is claimed is:

1. A preparation method of a trench type power semiconductor device, the preparation method comprising:
providing a semiconductor substrate comprising a bottom substrate and an epitaxial layer atop the bottom substrate;
etching the epitaxial layer to form an isolation trench in a termination area and active trenches in an active area, wherein an active to termination intermediate area is located between an outermost active trench close to the isolation trench and the isolation trench;
depositing a conductive material in the isolation trench and in the active trenches;
depositing an insulation passivation layer to cover the semiconductor substrate; and
etching through the insulation passivation layer corresponding to a mesa in the active to termination intermediate area and corresponding to a mesa in the active area to form a first contact hole passing through the insulation passivation layer and extending downward into the mesa of the active area and a second contact hole passing through the insulation passivation layer and extending downward into the mesa of the active to termination intermediate area;
wherein the first contact hole is deeper and wider than the second contact hole.

2. The preparation method of claim 1 , wherein the semiconductor substrate has a first conductive type, and wherein the preparation method further comprises
before depositing the insulation passivation layer, implanting dopants of a second conductive type opposite to the first conductive type into a top portion of the epitaxial layer to form a body layer of the second conductive type; and
implanting dopants of the first conductive type into a top portion of the body layer in the active area to form a source layer of the first conductive type.

3. The preparation method of claim 1 , wherein the step of etching through the insulation passivation layer comprises:
applying a mask covering the insulation passivation layer and at least forming a first opening and a second opening in the mask, wherein the first opening is wider than the second opening; and
etching through the second opening to form the second contact hole and etching through the first opening to form the first contact hole.

4. The preparation method of claim 1 , wherein the step of etching through the insulation passivation layer comprises:
applying a first mask atop the insulation passivation layer, at least forming a first opening in the first mask, and etching through the first opening to form the first contact hole; and
after stripping the first mask, applying a second mask atop the insulation passivation layer, forming a second opening in the second mask, and etching through the second opening to form the second contact hole; wherein
the first opening is wider than the second opening.

5. The preparation method of claim 1
wherein the semiconductor substrate has a first conductive type, and wherein the preparation method further comprises
before depositing the insulation passivation layer, implanting dopants of a second conductive type opposite to the first conductive type into a top portion of the epitaxial layer to form a body layer of the second conductive type; and
implanting dopants of the first conductive type into a top portion of the body layer in the active area to form a source layer of the first conductive type;

implanting dopants of a same conductive type and with higher doping concentration as the body layer into a respective body layer of the intermediate area and the active area through the first contact hole and the second contact hole to form a plurality of body contact implants, wherein
the first contact hole is deeper and wider than the second contact hole so that a depth and a diffusion range of a body contact implant of the plurality of body contact implants surrounding a bottom peripheral of the second contact hole are smaller than a depth and a diffusion range of the body contact implant of the plurality of body contact implants surrounding a bottom peripheral of the first contact hole.

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Ding Yongping
• Yilmaz Hamza
• Wang Xiaobin
• Bobde Madhur

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H01L29/402

  Electricity · mapped topic

• H01L29/0626 Primary

  Electricity · mapped topic

• H01L29/7811

  Electricity · mapped topic