High speed and low power circuit structure for barrel shifter

Patent metadata

Field	Value
Publication number	US-9996317-B2
Application number	US-201514611223-A
Country	US
Kind code	B2
Filing date	Jan 31, 2015
Priority date	Jun 29, 2012
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

First claim

What is claimed is:

1. A circuit for encoding selection signals to control selectors of a multi-stage barrel shifter, comprising:
a sign magnitude to 2's complement converter having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, wherein said sign magnitude to 2's complement converter uses a 2's complement of the input shift amount to generate a first decoder signal for controlling a first selector and to generate a second decoder signal for controlling a second selector.

2. The circuit of claim 1 wherein said sign magnitude to 2's complement converter computes an output result as the 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to the first decoder signal, and assigns a second portion of the output result to the second decoder signal.

3. The circuit of claim 2 adapted for a 64-bit barrel shifter wherein:
the input shift amount has 6 bits;
the output result has 6 bits;
the first decoder signal has 3 bits; and
the second decoder signal has 3 bits.

4. The circuit of claim 3 wherein said sign magnitude to 2's complement converter generates the first and second decoder signals using no more than three stages of gates.

5. The circuit of claim 1 wherein the input shift direction has a logical high value to indicate a shift direction to the right, and has a logical low value to indicate a shift direction to the left.

6. A barrel shifter comprising:
a sign magnitude to 2's complement converter circuit having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, wherein said sign magnitude to 2's complement converter circuit generates a first decoder signal and a second decoder signal;
a first decoder circuit which derives a first selection signal from the first decoder signal;
a second decoder circuit which derives a second selection signal from the second decoder signal;
a first selector controlled by the first selection signal which selects an intermediate shifted value from a first plurality of shifted values representing an operand value shifted by different integer multiples of a first shift level unit amount; and
a second selector controlled by the second selection signal which selects a raw shifted value from a second plurality of shifted values representing the intermediate shifted value shifted by different integer multiples of a second shift level unit amount.

7. The barrel shifter of claim 6 wherein said sign magnitude to 2's complement converter circuit computes an output result as a 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to the first decoder signal, and assigns a second portion of the output result to the second decoder signal.

8. The barrel shifter of claim 6 wherein said sign magnitude to 2's complement converter circuit has no more than three stages of gates.

9. The barrel shifter of claim 6 wherein said first decoder circuit and said second decoder circuit have identical constructions.

10. The barrel shifter of claim 6 wherein the input shift direction has a logical high value to indicate a shift direction to the right, and has a logical low value to indicate a shift direction to the left.

11. The barrel shifter of claim 6 wherein said first and second selectors use transfer gate multiplexers.

12. The barrel shifter of claim 6 , further comprising an output multiplexer for converting the raw shifted data into final shifted data.

13. In a barrel shifter which shifts an operand value in a single clock cycle using cascaded multiplexer selectors, the improvement comprising:
a sign magnitude to 2's complement converter circuit having a sign input which receives an input shift direction for a shift operation and having a magnitude input which receives an input shift amount for the shift operation, said sign magnitude to 2's complement converter circuit generating decoder signals for controlling the cascaded multiplexer selectors.

14. The improvement of claim 13 wherein said sign magnitude to 2's complement converter circuit computes an output result as a 2's complement of the input shift amount using the shift direction as a sign input, assigns a first portion of the output result to a first decoder signal, and assigns a second portion of the output result to a second decoder signal.

15. The improvement of claim 13 wherein the barrel shifter is adapted to shift a 64-bit operand value and said sign magnitude to 2's complement converter circuit generates the decoder signals using no more than three stages of gates.

Assignees

• Yasuda Takeo
• IBM

Inventors

• Yasuda Takeo

Classifications

• G06F5/015 Primary

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title

• G06F7/76

  Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data · CPC title