Selectively combinable shifters

Patent metadata

Field	Value
Publication number	US-9933996-B2
Application number	US-201314136754-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2012
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

An apparatus for mathematical manipulation is described allowing the selective combination of shifters to shift binary numbers of various widths. Selective combination allows on-the-fly adjustment of shifters from independent to coordinated shifting operations. Selective combination allows adjustable hardware-based shifting while saving space and resources. Multiple eight-bit shifters can be configured for a variety of operand widths, such as a 32-bit width, a 24-bit width, a 16-bit width, or an eight-bit width. Multiplexers route the appropriate input data to the appropriate shifters. Opcodes configure the shifters for the desired type of shift and a shifted result is generated.

First claim

What is claimed is:

1. An apparatus for mathematical manipulation comprising:
a first port coupled to a first shifter circuit wherein the first port has a first width;
a second port coupled to a second shifter circuit wherein:
the second port has a second width;
the second shifter circuit is configured to be selectively coupled to the first shifter circuit;
the first port and the second port are configured to be usable in combination to handle input of a binary number of a third width wherein the third width is less than or equal to a sum of the first width and the second width;
the first shifter circuit in combination with the second shifter circuit are configured to be usable to shift the binary number of the third width; and
the first shifter circuit is configured to shift a binary number of the first width and the second shifter circuit is configured to shift a binary number of the second width wherein the binary number of the first width and the binary number of the second width are different widths.

2. The apparatus of claim 1 wherein the first shifter circuit and the second shifter circuit are configured to be usable to shift by different amounts.

3. The apparatus of claim 1 wherein the first shifter circuit includes a barrel shifter.

4. The apparatus of claim 1 wherein the first shifter circuit includes configuration logic to enable simultaneous shifting of more than one bit.

5. The apparatus of claim 1 wherein the first shifter circuit and the second shifter circuit are configured to be usable to shift independently of one another.

6. The apparatus of claim 1 further comprising a first shift-in port for the first shifter circuit.

7. The apparatus of claim 6 wherein the first shifter circuit is configured to be usable to pad a shifted number with zeros.

8. The apparatus of claim 7 wherein the first shifter circuit, in combination with the second shifter circuit, is used to shift the binary number of the third width by a shift value greater than the second width.

9. The apparatus of claim 8 wherein the first shifter circuit, in combination with the second shifter circuit, pads the shifted number with zeros.

10. The apparatus of claim 1 further comprising a second shift-in port for the second shifter circuit.

11. The apparatus of claim 1 further comprising additional configuration logic to enable shifting of bits from the second shifter circuit to the first shifter circuit.

12. The apparatus of claim 1 wherein an opcode is used to configure the first shifter circuit and the second shifter circuit to enable shifting of the binary number of the third width.

13. The apparatus of claim 1 further comprising a processing element to control at least the first shifter circuit.

14. The apparatus of claim 1 further comprising a processing element to control at least the second shifter circuit.

15. A method of logical calculation comprising:
configuring a first shifter circuit and a second shifter circuit wherein:
the first shifter circuit is coupled to a first port that has a first width;
the second shifter circuit is coupled to a second port that has a second width wherein:
the second shifter circuit is configured to be selectively coupled to the first shifter circuit;
the first port and the second port are configured to be usable in combination to handle input of a binary number of a third width wherein the third width is less than or equal to a sum of the first width and the second width;
the first shifter circuit in combination with the second shifter circuit are configured to be usable to shift the binary number of the third width; and
the first shifter circuit is configured to shift a binary number of the first width and the second shifter circuit is configured to shift a binary number of the second width wherein the binary number of the first width and the binary number of the second width are different widths.

16. A computer implemented method for implementation of a logical calculation apparatus comprising:
implementing a first shifter circuit coupled to a first port included in logic on a semiconductor chip, wherein the first port has a first width;
implementing a second shifter circuit coupled to a second port included in the logic on a semiconductor chip, wherein:
the second port has a second width;
the second shifter circuit is configured to be selectively coupled to the first shifter circuit;
the first port and the second port are configured to be usable in combination to handle input of a binary number of a third width wherein the third width is less than or equal to a sum of the first width and the second width;
the first shifter circuit in combination with the second shifter circuit are configured to be usable to shift the binary number of the third width; and
the first shifter circuit is configured to shift a binary number of the first width and the second shifter circuit is configured to shift a binary number of the second width wherein the binary number of the first width and the binary number of the second width are different widths.

17. A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus, the computer program product comprising code which causes one or more processors to perform operations of:
implementing a first shifter circuit coupled to a first port included in logic on a semiconductor chip, wherein the first port has a first width;
implementing a second shifter circuit coupled to a second port included in the logic on a semiconductor chip, wherein:
the second port has a second width;
the second shifter circuit is configured to be selectively coupled to the first shifter circuit;
the first port and the second port are configured to be usable in combination to handle input of a binary number of a third width wherein the third width is less than or equal to a sum of the first width and the second width;
the first shifter circuit in combination with the second shifter circuit are configured to be usable to shift the binary number of the third width; and
the first shifter circuit is configured to shift a binary number of the first width and the second shifter circuit is configured to shift a binary number of the second width wherein the binary number of the first width and the binary number of the second width are different widths.

18. A computer system for implementation of a logical calculation apparatus comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
implement a first shifter circuit coupled to a first port included in logic on a semiconductor chip, wherein the first port has a first width;
implement a second shifter circuit coupled to a second port included in the logic on a semiconductor chip, wherein:
the second port has a second width;
the second shifter circuit is configured to be selectively coupled to the first shifter circuit;
the first port and the second port are configured to be usable in combination to handle input of a binary number of a third width wherein the third width is less than or equal to a sum of the first width and the second width;
the first shifter circuit in combination with the second shifter circuit are configured to be usable to shift the binary number of the third width; and
the first shifter circuit is configured to shift a binary number of the first width and the second shifter circuit is configured to shift a binary number of the second width wherein the binary num

Assignees

• Wave Semiconductor Inc
• Wave Computing Inc

Inventors

• Chaudhuri Samit

Classifications

• G06F5/01 Primary

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G06F5/015 Primary

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title