Data processing device, data processing method, and computer program

Patent metadata

Field	Value
Publication number	US-10061558-B2
Application number	US-201715446045-A
Country	US
Kind code	B2
Filing date	Mar 1, 2017
Priority date	Mar 14, 2013
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.

First claim

What is claimed is:

1. A data processing device comprising:
an input terminal and an output terminal;
a first switch comprising a first terminal electrically connected to the input terminal, and a second terminal electrically connected to the output terminal;
a second switch comprising a third terminal electrically connected to the input terminal, and a fourth terminal;
a third switch comprising a fifth terminal electrically connected to the second terminal, and a sixth terminal; and
a signal storing circuit electrically connected to the fourth terminal and the sixth terminal,
wherein:
the data processing device is configured to select at least a first operation, a second operation, and a third operation,
the first operation comprises the steps of outputting a data input from the input terminal to the output terminal, and storing the data in the signal storing circuit,
the second operation comprises the step of outputting a data input from the input terminal to the output terminal without storing the data in the signal storing circuit, and
the third operation comprises the step of outputting a data stored in the signal storing circuit to the output terminal.

2. The data processing device according to claim 1 , further comprising:
a memory; and
a logic circuit configured to perform an arithmetic processing on a data,
wherein after the arithmetic processing, the data is transferred from the memory and input to the first switch.

3. The data processing device according to claim 2 ,
wherein:
when a plurality of processes are performed in the data processing device, the data processing device is configured to perform at least a first processing, a second processing, and a third processing,
the first processing comprises the step of selecting a most frequently performed process from the plurality of processes,
the second processing comprises the step of storing a result of the most frequently performed process in the signal storing circuit when the most frequently performed process is performed for the first time, and
the third processing comprises the step of outputting the result stored in the signal storing circuit when the most frequently performed process is performed for the second time.

4. The data processing device according to claim 3 ,
wherein:
the data processing device is configured to further perform a fourth processing,
the fourth processing comprises the step of performing a process different from the most frequently performed process, and
the fourth processing is performed between the second processing and the third processing.

5. The data processing device according to claim 1 , wherein each of the first switch, the second switch, and the third switch is a transistor, a transfer gate, a transmission gate, a three-state buffer, or a three-state inverter.

6. The data processing device according to claim 1 , wherein the signal storing circuit is a capacitor or a latch circuit.

7. The data processing device according to claim 2 , wherein the logic circuit is a shifter.

Assignees

• Semiconductor Energy Lab

Inventors

• Ohshima Kazuaki

Classifications

• H03K17/04

  Modifications for accelerating switching · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K3/356

  Bistable circuits · CPC title

• H03K3/037

  Bistable circuits · CPC title

• G06F5/015 Primary

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title