Enhanced Multiply Accumulate Device For Neural Networks
US-2021382690-A1 · Dec 9, 2021 · US
having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence)
having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F5/015 |
| Official title | {having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence)} |
| Display label | having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) |
| Total patents | 96 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 4 |
| 2016 | 4 |
| 2017 | 4 |
| 2018 | 18 |
| 2019 | 9 |
| 2020 | 13 |
| 2021 | 8 |
| 2022 | 6 |
| 2023 | 13 |
| 2024 | 8 |
| 2025 | 5 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-11196953-B2 · Dec 7, 2021 · US
Compute optimizations for neural networks
US-2021373886-A1 · Dec 2, 2021 · US
System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit
US-2021263994-A1 · Aug 26, 2021 · US
Compute optimizations for neural networks using bipolar binary weight
US-11074072-B2 · Jul 27, 2021 · US
Low latency matrix multiply unit
US-2021209193-A1 · Jul 8, 2021 · US
System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit
US-11036829-B2 · Jun 15, 2021 · US
Low latency matrix multiply unit
US-10970362-B2 · Apr 6, 2021 · US
Apparatus and method for transforming matrix, and data processing system
US-2020412382-A1 · Dec 31, 2020 · US
Reconfigurable segmented scalable shifter
US-10877729-B2 · Dec 29, 2020 · US
Low latency matrix multiply unit
US-2020327186-A1 · Oct 15, 2020 · US
Hybrid matrix multiplication pipeline
US-2020272687-A1 · Aug 27, 2020 · US
Reconfigurable segmented scalable shifter
US-2020249909-A1 · Aug 6, 2020 · US
Low latency matrix multiply unit
US-2020226202-A1 · Jul 16, 2020 · US
Low latency matrix multiply unit
US-10698974-B2 · Jun 30, 2020 · US
Low latency matrix multiply unit
US-10698976-B2 · Jun 30, 2020 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-2020154072-A1 · May 14, 2020 · US
Low latency matrix multiply unit
US-10635740-B2 · Apr 28, 2020 · US
System, Method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit
US-10572569-B2 · Feb 25, 2020 · US
System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit
US-2020057790-A1 · Feb 20, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F5/015?
- CPC G06F5/015 is the Cooperative Patent Classification code for “having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence).”
- How many patents are filed under CPC G06F5/015 (having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence))?
- Our database includes 96 publications tagged with this CPC code.
- Is patent activity under CPC G06F5/015 growing?
- Publication counts under this code: 8 in 2024 vs 5 in 2025 (latest complete years).