Method and system of measuring semiconductor device and method of fabricating semiconductor device using the same

US9991174B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9991174-B2
Application numberUS-201414520477-A
CountryUS
Kind codeB2
Filing dateOct 22, 2014
Priority dateJan 17, 2014
Publication dateJun 5, 2018
Grant dateJun 5, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, and calculating a measurement target parameter using a difference between the first and second volumes.

First claim

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What is claimed is: 1. A method of fabricating a semiconductor device, comprising: forming a device isolation layer on a substrate to define an active pattern, wherein the active pattern is a portion of the substrate that is penetrating through the device isolation laver; etching the substrate and the device isolation layer to form a trench crossing the active pattern, wherein the trench is formed in the substrate; obtaining a first measurement data from the trench using a scanning electron microscope and an optical scatterometry instrument, the scanning electron microscope including a first chuck and the optical scatterometry instrument including a second chuck, the obtaining the first measurement data including measuring a width of the trench and measuring a depth of the trench; forming a gate pattern in the trench, wherein the gate pattern fills a lower region of the trench and exposes an upper region of the trench; obtaining a second measurement data from the gate pattern using an X-ray fluorescence analysis instrument; obtaining a first volume of the trench using the first measurement data; obtaining a second volume of the gate pattern using the second measurement data; obtaining a measurement target parameter using a difference between the first and second volumes, wherein the measurement target parameter is a distance between a top surface of the gate pattern and a top surface of the substrate; and examining whether the measurement target parameter is within an allowed range. 2. The method of claim 1 , wherein the first measurement data is obtained using a non-destructive testing method, the width of the trench is measured by the scanning electron microscope (SEM)instrument, and the depth of the trench is measured by the optical scatterometry instrument. 3. The method of claim 1 , wherein the obtaining the second measurement data comprises measuring mass of an element contained in the gate pattern. 4. The method of claim 3 , wherein the second measurement data is obtained using a non-destructive testing method, and the mass of the element contained in the gate pattern is measured by the X-ray fluorescence analysis instrument. 5. The method of claim 3 , wherein the obtaining the measurement target parameter comprises operating a calculation module included in a computer system, the calculation module is configured to calculate the first volume, the second volume, and the measurement target parameter, the first volume being calculated by multiplying the width of the trench, the depth of the trench, and a first constant, the second volume being calculated by multiplying the mass of the element contained in the gate pattern by a second constant, and the measurement target parameter being calculated by dividing a third volume, which is obtained by subtracting the second volume from the first volume, by multiplication of the width of the trench and the first constant. 6. The method of claim 5 , wherein the obtaining of the measurement target parameter further comprises operating a verification module included in the computer system, the verification module is configured to determine the first and second constants to reduce an error between the measurement target parameter calculated by the calculation module and reference data. 7. The method of claim 1 , wherein the forming of the gate pattern comprises: forming a gate layer on the substrate to fill the trench; and etching the gate layer, wherein if the examining determines the measurement target parameter is smaller than the allowed range, repeating the etching the gate layer. 8. A method of determining a physical parameter of a semiconductor device under manufacture, comprising: performing non-destructive measuring of at least a first physical parameter and a second physical parameter of structures in the semiconductor device under manufacture using a scanning electron microscope, an optical scatterometry instrument, and an X-ray fluorescence analysis instrument, each of the scanning electron microscope, the optical scatterometry instrument, and the X-ray fluorescence analysis instrument including a separate chuck configured to support the semiconductor device, the first physical parameter including a measurement of a recess region, and the second physical parameter including a measurement of a conductive pattern filling a portion of the recess region; and determining a third physical parameter of the structures based on data generated from the performing of the non-destructive measuring.

Assignees

Inventors

Classifications

  • H10P74/203Primary

    Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth · CPC title

  • Patterns showing highly reflecting parts, e.g. metallic elements · CPC title

  • using a comparative method · CPC title

  • Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20) · CPC title

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What does patent US9991174B2 cover?
The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, an…
Who is the assignee on this patent?
Leem Choonshik, Lee Jihye, Kim Deokyong, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10P74/203. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 05 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).