Semiconductor structure and method for manufacturing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-9989703-B2
Application number	US-201615379523-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Nov 30, 2012
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure comprising:
providing a silicon substrate;
integrating electronic and photonic components with the silicon substrate to form a processed complementary metal-oxide semiconductor (CMOS) layer that overlies the silicon substrate and includes the electronic and photonic components;
depositing a passivation layer that overlies the processed CMOS layer and the electronic and photonic components therein;
depositing a dielectric interlayer over the passivation layer;
bonding an interface layer comprising a III-V material to a surface of the dielectric interlayer such that the electronic and photonic components of the processed CMOS layer are communicatively connected to the bonded interface layer by electrical and photonic contacts that penetrate the dielectric interlayer;
removing an inverted substrate that is adhered to and overlies the bonded interface layer; and
epitaxially growing a layer of the III-V material from the bonded interface layer between 120° C. and 650° C., wherein the electronic and photonic components of the processed CMOS layer are front-end components and are capable of operation after exposure to temperatures between 120° C. and 650° C.

2. The method of manufacturing a semiconductor structure of claim 1 , wherein the epitaxially grown layer of the III-V material comprises a laser.

3. The method of manufacturing a semiconductor structure of claim 1 , wherein the epitaxially grown layer of the III-V material comprises an optical amplifier.

4. The method of manufacturing a semiconductor structure of claim 1 , wherein the epitaxially grown layer of the III-V material comprises a light-emitting diode.

5. The method of manufacturing a semiconductor structure of claim 1 , wherein the passivation layer comprises silicon nitride.

6. The method of manufacturing a semiconductor structure of claim 1 , wherein the dielectric interlay comprises silicon dioxide.

7. The method of manufacturing a semiconductor structure of claim 1 , wherein the electronic and photonic components of the processed CMOS layer comprise one or more silicon-based waveguides.

8. The method of manufacturing a semiconductor structure of claim 1 , wherein the bonded interface layer is bonded to the surface of the dielectric interlayer between 200° C. and 300° C.

Assignees

• IBM

Inventors

• Czornomaz Lukas
• Fompeyrine Jean
• Hofrichter Jens
• Offrein Bert Jan
• Richter Mirja

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L2223/54426

  Electricity · mapped topic

• G02B6/12004

  Combinations of two or more optical elements · CPC title