Semiconductor structure and method for manufacturing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-2016334574-A1
Application number	US-201314442240-A
Country	US
Kind code	A1
Filing date	Nov 27, 2013
Priority date	Nov 30, 2012
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

First claim

1 - 24 . (canceled)

25 . A semiconductor structure comprising:
a processed semiconductor substrate including active electronic components; a dielectric layer covering, at least partially, the processed semiconductor substrate; and an interface layer which is suitable for growing optically active material on the interface layer, wherein the interface layer is bonded to the dielectric layer, wherein the interface layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

26 . The semiconductor structure of claim 25 , wherein the dielectric layer has a thickness between 10 nm and 1 μm.

27 . The semiconductor structure of claim 25 , wherein the interface layer is an optically active layer or a layer on which the optically active layer is grown.

28 . The semiconductor structure of claim 25 , wherein the processed semiconductor substrate includes at least one of drive electronics, a transistor, memory, an amplifier circuit, and at least one of silicon photonics components, an optical waveguide, a grating coupler, a modulator, a multiplexer, a de-multiplexer, a ring resonator, and a directional coupler.

29 . The semiconductor structure of claim 25 , wherein the processed semiconductor substrate is at least one part of a processed CMOS wafer that includes at least one of front-end electronics and front-end photonic components.

30 . The semiconductor structure of claim 25 , wherein one of the interface layer and an optically active layer includes at least one of a compound semiconductor material having a direct band-gap and germanium.

31 . The semiconductor structure of claim 25 , wherein one of the interface layer and an optically active layer includes at least one of an optical waveguide, a modulator, a polarization rotator, a grating coupler, a photo detector, a photo diode, a quantum well stack, a light source, a laser, a dielectric Bragg reflector laser, a distributed feedback laser, and a vertical cavity surface emitting laser.

32 . The semiconductor structure of claim 25 , wherein the interface layer is a seed layer having a lattice constant suitable for successive growth of optically active material.

33 . The semiconductor structure of claim 25 , wherein the dielectric layer is a first interlayer dielectric.

34 . A method for fabricating a semiconductor structure comprising:
providing a processed semiconductor substrate that includes active electronic components; depositing a dielectric layer that covers, at least partially, the processed semiconductor substrate; bonding an interface layer to the dielectric layer, wherein the interface layer is suitable for growing optically active material on the interface layer; and connecting the interface layer and the processed semiconductor substrate with each other through the dielectric layer by at least one of electrical and optical contacts.

35 . The method of claim 34 , wherein providing the processed semiconductor substrate includes providing a processed CMOS wafer that includes at least one of front-end electronics and front-end photonic components.

36 . The method of claim 34 , wherein the interface layer includes at least one of a compound semiconductor material having a direct band-gap and germanium.

37 . The method of claim 34 , further comprising:
providing the interface layer on a substrate; and removing the substrate from the interface layer after bonding the interface layer to the dielectric layer.

38 . The method of claim 34 , wherein bonding the interface layer to the dielectric layer is performed after front-end-of line processing of the processed semiconductor substrate, and wherein the dielectric layer is a first interlayer dielectric.

39 . The method of claim 34 , further comprising:
before bonding the interface layer to the dielectric layer, covering the interface layer with a cladding layer; and bonding the cladding layer with the dielectric layer.

40 . The method of claim 34 , further comprising:
before depositing the dielectric layer, forming protruding contacts on the processed semiconductor substrate.

41 . The method of claim 34 , further comprising:
after bonding the interface layer to the dielectric layer, employing the interface layer as a seed layer and growing optically active material onto the seed layer for forming an optically active layer.

42 . The method of claim 34 , wherein bonding the interface layer to the dielectric layer is performed at temperatures between 20° C. and 600° C.

43 . The method of claim 34 , further comprising:
after bonding the interface layer to the dielectric layer, structuring one of the interface layer and an optically active layer on the interface layer for forming photonic components.

44 . The method of claim 43 , wherein the processed semiconductor substrate includes alignment markers, and wherein structuring one of the interface layer and the optically active layer is performed by at least one structuring tool that is aligned relative to the alignment markers.

Assignees

• IBM

Inventors

• Czornomaz Lukas
• Fompeyrine Jean
• Hofrichter Jens
• Offrein Bert Jan
• Richter Mirja

Classifications

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• H10F99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10F71/00 Primary

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title