Integrated multi-chip module optical interconnect platform

Patent metadata

Field	Value
Publication number	US-9620489-B2
Application number	US-201414298875-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Dec 6, 2011
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity. For example, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies.

First claim

What is claimed is:

1. An integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies, comprising:
a carrier substrate structured to form openings on a top side of the carrier substrate;
semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and at least one integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and
planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies.

2. The device as in claim 1 , wherein:
the optical waveguides in the planar layers are configured to provide direct optical routing amongst photonic devices associated with different semiconductor integrated circuit dies in different openings on the carrier substrate without converting an optical signal to be routed into an electrical signal.

3. The device as in claim 1 , wherein:
each semiconductor integrated circuit die includes conductive wires or solder bumps for electrical connection of a respective integrated circuit formed on a respective semiconductor substrate without having optical interconnects.

4. The device as in claim 1 , wherein:
each semiconductor integrated circuit die includes a top dielectric layer formed over a respective integrated circuit formed on top of a respective semiconductor substrate, and the top dielectric layer has a top surface that is substantially coplanar with the top side of the carrier substrate.

5. The device as in claim 1 , wherein:
the planar layers include
a lower dielectric layer over the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate;
an optical waveguide formed on top of the lower dielectric layer; and
a top dielectric layer formed on top of the optical waveguide and the lower dielectric layer to enclose the optical waveguide between the lower and top dielectric layers.

6. The device as in claim 1 , wherein:
the optical waveguides in the planar layers include an optical waveguide having an optical ring.

7. The device as in claim 1 , comprising:
a central processing unit (CPU) on one of the semiconductor integrated circuit dies to enable communication to and from the CPU via one or more of the optical waveguides.

8. The device as in claim 7 , further comprising:
a memory device in communication with the CPU.

9. The device as in claim 8 , wherein:
the optical waveguides are connected to provide high-bandwidth communications between the CPU and the memory device.

10. The device as in claim 7 , further comprising:
a graphic processing unit (GPU) in communication with the CPU.

11. The device as in claim 10 , wherein:
the optical waveguides are connected to provide high-bandwidth communications between the CPU and the GPU.

12. The device as in claim 7 , wherein:
the optical waveguides are connected to provide high-bandwidth communications between the CPU and another device on the carrier substrate.

13. The device as in claim 1 , wherein:
the planar layers include multiple optical layers.

14. The device as in claim 13 , wherein:
the multiple optical layers in the planar layers include an active optical layer that includes at least one optically active device which can be controlled by control signal to change or modify a property of an optical signal.

15. The device as in claim 1 , wherein:
the semiconductor integrated circuit dies include complementary metal-oxide-semiconductor (CMOS) circuits.

16. The device as in claim 1 , wherein:
each semiconductor integrated circuit die includes conductive vias to provide an electrical contact for the integrated circuit with an active optical layer that includes at least one optically active device which can be controlled by control signal to change or modify a property of an optical signal.

17. The device as in claim 1 , wherein:
each semiconductor integrated circuit dies is fixed to a bottom surface of a respective opening of the carrier substrate via oxide bonding between a respective semiconductor substrate and the bottom surface of the respective opening of the carrier substrate.

18. The device as in claim 1 , wherein:
each semiconductor integrated circuit dies is fixed to a bottom surface of a respective opening of the carrier substrate via oxide bonding by a flowable oxide layer formed between a respective semiconductor substrate and the bottom surface of the respective opening of the carrier substrate.

19. A method for providing optical interconnects to various devices on an integrated platform, comprising:
providing different integrated circuits on separated semiconductor integrated circuit dies;
embedding the semiconductor integrated circuit dies in openings of a carrier substrate to fix each semiconductor die on a bottom surface of the carrier substrate in each opening to make a top surface of each semiconductor integrated circuit die substantially coplanar with a top side of the carrier substrate;
forming planar layers on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies to enable direct optical communication from one die to another die without converting an optical signal into an electrical signal when communicating between two dies.

20. The method as in claim 19 , comprising:
including in the planar layers multiple optical layers to provide optical interconnects in each of the multiple optical layers.

21. The method as in claim 19 , wherein:
the multiple optical layers in the planar layers include an active optical layer.

22. The method as in claim 19 , wherein:
forming optical rings in the planar layers to be optically coupled to the optical waveguides.

23. A method for fabricating an integrated platform that supports different devices and optical interconnects for the different devices, comprising:
processing a carrier substrate to form openings on a top side of the carrier substrate;
forming an adhesive layer in a bottom surface in each opening of the carrier substrate;
placing semiconductor integrated circuit dies over bottom surfaces of the openings of the carrier substrate so that each semiconductor integrated circuit die is fixed in position by the adhesive layer, wherein each semiconductor integrated circuit die includes a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die is structured to have a top surface substantially coplanar with the top side of the carrier substrate;
forming a sacrificial layer over the top surfaces of the semiconductor integrated circuit die

Assignees

• Univ Cornell

Inventors

• Lipson Michal
• Lee Yoon Ho

Classifications

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• G02B6/12007

  forming wavelength selective elements, e.g. multiplexer, demultiplexer · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• H01L31/0232

  Electricity · mapped topic