Analog-to-digital converter verification using quantization noise properties

Patent metadata

Field	Value
Publication number	US-9985646-B1
Application number	US-201715787387-A
Country	US
Kind code	B1
Filing date	Oct 18, 2017
Priority date	Oct 18, 2017
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

First claim

What is claimed is:

1. A method for identifying errors in a noise-shaping analog-to-digital converter (ADC), comprising:
determining a first characteristic in a sequence of pulses output by a noise-shaping modulator that have a pulse width within a first pulse width band;
determining a second characteristic in the sequence of pulses output by the noise-shaping modulator that have a pulse width within a second pulse width band,
wherein the second pulse width band includes pulses that are wider than at least some of the pulses in the first pulse width band;

evaluating the first characteristic in the sequence of pulses within the first pulse width band relative to the second characteristic in the sequence of pulses within the second pulse width band; and
indicating an ADC error based on a determination that the first characteristic in the sequence of pulses within the first pulse width band is outside of a threshold relative to the second characteristic in the sequence of pulses within the second pulse width band.

2. An error checking system for an analog-to-digital converter (ADC), comprising:
a first pulse characteristic evaluator to determine a first characteristic in a sequence of pulses produced by the ADC;
a comparison subsystem to compare the first characteristic in the sequence of pulses with a first threshold range bounded by at least one of a first minimum value and a first maximum value; and
an error identification subsystem to indicate an ADC error based on a determination that the first characteristic in the sequence of pulses is outside of the first threshold range.

3. The error checking system of claim 2 , wherein the first characteristic comprises an average pulse width in the sequence of pulses.

4. The error checking system of claim 2 , wherein the first characteristic comprises a number of transitions in the sequence of pulses.

5. The error checking system of claim 2 , wherein the error identification subsystem is configured to indicate an ADC error by ceasing to provide a verification signal.

6. The error checking system of claim 2 , wherein the error identification subsystem is configured to indicate an ADC error by transmitting an error signal.

7. The error checking system of claim 2 , wherein the comparison subsystem is configured to compare the first characteristic in the sequence of pulses with a nonzero, first minimum value and a nonzero, first maximum value.

8. The error checking system of claim 2 , further comprising:
an input magnitude module to calculate a magnitude of an input signal to the noise-shaping modulator; and
a noise limit calculation module to determine at least one of the first minimum value and the first maximum value based on the calculated magnitude of the input signal to the ADC.

9. The error checking system of claim 2 , further comprising:
a noise limit calculation module to determine at least one of the first minimum value and the first maximum value based on at least one of: a measurement, a calculation, and a simulation associated with the first characteristic.

10. The error checking system of claim 2 , further comprising:
a noise limit calculation module to determine at least one of the first minimum value and the first maximum value based, at least in part, on at least one of: a temperature measurement, a frequency measurement, a characteristic of the ADC, a characteristic of an environment of the ADC, a characteristic of a system in which the ADC is employed, and a characteristic of an environment of a system in which the ADC is employed.

11. The error checking system of claim 2 , wherein the ADC comprises a noise-shaping ADC, and wherein the signal generated by the ADC comprises the output of a noise-shaping modulator.

12. The error checking system of claim 11 , wherein the noise-shaping modulator comprises at least one of:
a one-bit delta-sigma modulator,
a three-bit delta-sigma modulator, and
a second order delta-sigma modulator.

13. The error checking system of claim 2 , wherein the ADC comprises a successive approximation register (SAR) ADC.

14. The error checking system of claim 2 , wherein the comparison subsystem comprises one of: (i) one or more differential amplifiers; (ii) a software module; and (iii) at least a portion of a field-programmable gate array; and
wherein the error identification subsystem comprises one of: (i) one or more logic gates; (ii) a software module; and (iii) at least a portion of a field-programmable gate array.

15. The error checking system of claim 2 , wherein the first pulse characteristic evaluator comprises a first pulse counter, and wherein the first characteristic comprises a number of pulses in the sequence of pulses within a first pulse width band.

16. The error checking system of claim 15 , wherein the first pulse width band comprises one of:
pulses having a width of 1 sample cycle; and
pulses having a width between 1 sample cycle and 4 sample cycles.

17. The error checking system of claim 15 , further comprising,
a second pulse counter to determine the number of pulses in the sequence of pulses produced by the ADC that have a pulse width within a second pulse width band, wherein the second pulse width band includes pulses that are wider than at least some of the pulses in the first pulse width band;
a third pulse counter to determine the number of pulses in the sequence of pulses produced by the ADC that have a pulse width within a third pulse width band, wherein the third pulse width band includes pulses that are wider than at least some of the pulses in the second pulse width band;
wherein the comparison subsystem is configured to:
compare the number of pulses in the sequence of pulses within the second pulse width band with a second threshold range bounded by at least one of a second minimum value and a second maximum value, and
compare the number of pulses in the sequence of pulses within the third pulse width band with a third threshold range bounded by at least one of a third minimum value and a third maximum value; and

wherein the error identification subsystem is configured to indicate an ADC error based on a determination that any one of:
(i) the first number of pulses in the sequence of pulses within the first pulse width band is outside of the first threshold range,
(ii) the second number of pulses in the sequence of pulses within the second pulse width band is outside of the second threshold range, and
(iii) the third number of pulses in the sequence of pulses within the third pulse width band is outside of the third threshold range.

18. The error checking system of claim 17 , wherein the first pulse width band comprises pulses having a width between 1 sample cycle and 4 sample cycles,
wherein the second pulse width band comprises pulses having a width between 5 sample cycles and 8 sample cycles; and
wherein the third pulse width band comprises pulses having a width between 9 sample cycles and 16 sample cycles.

19. An error checking system for an analog-to-digital converter (ADC), comprising:
at least one pulse evaluator to:
determine a first characteristic in a sequence of pulses produced by the ADC that have a pulse width within a first pulse width band, and
determine a second characteristic in the sequence of pulses produced by the ADC that have a pulse width within a second pulse width band, wherein the second pulse width band includes pulses that are wider than at least some of the pulses in the first pulse width band;

a comparison subsystem to compare the first characteristic i

Assignees

• Schweitzer Engineering Lab Inc

Inventors

• Mallett Travis C

Classifications

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• H03M3/378 Primary

  Testing · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title