Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter

Patent metadata

Field	Value
Publication number	US-9490818-B2
Application number	US-201414448447-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Nov 27, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

First claim

What is claimed is:

1. A method comprising:
performing nonlinear quantization noise cancellation to generate a digital representation of a phase error with reduced quantization noise, the phase error corresponding to a time difference between a feedback signal of a fractional-N phase-locked loop (PLL) and a reference signal;
performing the nonlinear quantization noise cancellation in an analog domain to generate an analog representation of the phase error with reduced quantization noise;
converting the analog representation to a digital representation of the phase error with reduced quantization noise; and
performing cancellation on the digital representation based on residual error associated with the cancellation in the analog domain to generate a second digital representation with further reduced noise.

2. The method as recited in claim 1 further comprising:
introducing a non-linear component into an analog phase error representation in a time-to-voltage converter in the PLL.

3. A method comprising:
performing nonlinear quantization noise cancellation to generate a digital representation of a phase error with reduced quantization noise, the phase error corresponding to a time difference between a feedback signal of a fractional-N phase-locked loop (PLL) and a reference signal,
wherein performing the nonlinear quantization noise cancellation further comprises multiplying a quantization error based signal by a polynomial and supplying a multiplied signal, the quantization error based signal based on a residue signal from a first delta sigma modulator controlling a divider value for a feedback divider in the fractional-N PLL.

4. The method as recited in claim 3 further comprising:
updating coefficient values of the polynomial with a first update time period during initial operation of the quantization noise cancellation; and
updating the coefficient values of the polynomial with a second update time period greater than the first update time period during steady state operation of the quantization noise cancellation.

5. The method as recited in claim 3 further comprising forming the quantization error based signal by summing a dither signal with the residue signal.

6. The method as recited in claim 3 wherein the polynomial is a third order polynomial.

7. The method as recited in claim 3 further comprising:
supplying the multiplied signal to a second delta sigma modulator and generating a quantized version of the multiplied signal and a second residue signal corresponding to a residual error of a digital to analog converter;
supplying the quantized version of the multiplied signal to the digital to analog converter and generating an analog representation of the quantized version of the multiplied signal;
combining the analog representation of the quantized version of the multiplied signal with an analog representation of the phase error to reduce quantization noise in the analog representation of the phase error and generate an analog representation of the phase error with reduced quantization noise; and
supplying the analog representation of the phase error with reduced quantization noise to an analog to digital converter and generating the digital representation of the phase error.

8. The method as recited in claim 7 further comprising:
combining a first signal based on the second residue signal with a second signal corresponding to the digital representation of the phase error to generate a second digital representation of the phase error with further reduced quantization noise; and
controlling a frequency of an oscillator of the fractional-N PLL based on the second digital representation of the phase error.

9. The method as recited in claim 8 further comprising:
generating the second signal using a compensation filter to compensate for memory effect of a capacitor filter formed by capacitors used in sampling the analog representation of the phase error with reduced quantization noise.

10. The method as recited in claim 9 further comprising:
setting the quantized version of the multiplied signal to a constant value; and
determining coefficient values of the compensation filter with the quantized version of the multiplied signal set to the constant value.

11. A fractional-N phase-locked loop (PLL) comprising:
a nonlinear time to digital converter to generate a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal; and
a nonlinear quantization noise cancellation circuit coupled to supply a correction signal to the time to digital converter to cause the time to digital converter to generate the digital representation of the phase error with reduced quantization noise;
wherein the nonlinear time to digital converter further comprises,
a resistor-based or current-based charge pump controlled by a phase detector to create a voltage corresponding to the phase error that is combined with the correction signal; and
an analog to digital converter coupled to the charge pump to generate the digital representation of the phase error with reduced quantization noise.

12. The fractional-N PLL as recited in claim 11 further comprising:
a delta sigma modulator supplying a divider control signal for the fractional-N PLL and a first residue signal corresponding to a quantization error associated with the delta sigma modulator;
a feedback divider coupled to receive the divider control signal and an output of a controlled oscillator of the PLL and supply the feedback signal; and
wherein the nonlinear quantization noise cancellation circuit includes a multiplier circuit to multiply a quantization error signal by a polynomial and supply a multiplied signal, the quantization error signal based on the first residue signal.

13. The fractional-N PLL as recited in claim 12 wherein the nonlinear quantization noise cancellation circuit is configured to update coefficient values of the polynomial with a first update time period during a period of operation of the quantization noise cancellation and is configured to update the coefficent values of the polynomial with a second update time period during another period of operation, the second update time period being greater than the first update time period.

14. The fractional-N PLL as recited in claim 12 further comprising a summing circuit coupled to sum a dither signal with the first residue signal to generate the quantization error signal.

15. The fractional-N PLL as recited in claim 12 wherein the polynomial is a third order polynomial.

16. The fractional-N PLL as recited in claim 12 further comprising:
a second delta sigma modulator coupled to receive the multiplied signal and to generate a quantized version of the multiplied signal and a second residue signal;
a digital to analog converter coupled to receive the quantized version of the multiplied signal and generate an analog representation of the quantized version of the multiplied signal as the correction signal; and
wherein the analog representation of the quantized version of the multiplied signal and the voltage corresponding to the phase error are combined in the time to digital converter to generate an analog representation of the phase error with reduced quantization noise.

17. The fractional-N PLL as recited in claim 16 further comprising a summing circuit coupled to combine a first signal based on the second residue signal and a second signal based on the digital representation of the phase error, to generate a residual phase error signal having f

Assignees

• Silicon Lab Inc

Inventors

• Perrott Michael H

Classifications

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M7/3004

  Digital delta-sigma modulation · CPC title

• H03M3/358

  of non-linear distortion, e.g. instability (avoiding instability by structural design H03M3/44) · CPC title