Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

Patent metadata

Field	Value
Publication number	US-9520381-B2
Application number	US-201514592576-A
Country	US
Kind code	B2
Filing date	Jan 8, 2015
Priority date	Aug 29, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

First claim

What is claimed is:

1. A semiconductor device comprising:
a multilayer chip including a first semiconductor chip and a second semiconductor chip that are bonded together, wherein
a first electrode pad is provided on a principal surface of the first semiconductor chip,
a first bump is provided on the first electrode pad,
a second bump is provided on a principal surface of the second semiconductor chip and is bonded to the first bump,
the first electrode pad has an opening extending through the first electrode pad, the opening formed by removing a center portion of the first electrode pad,
the opening and an entire peripheral portion of the opening form a stepped shape, and
the first bump having a recessed portion that is recessed at a center thereof, in plan view immediately above the opening of the first electrode pad, the recessed portion covers the stepped shape, and the recessed portion conforms to a flat portion of the first electrode pad.

2. The semiconductor device of claim 1 , wherein the first electrode pad has a hollow cylindrical shape in plan view.

3. The semiconductor device of claim 1 , wherein the first electrode pad has a slit in the peripheral portion.

4. The semiconductor device of claim 1 , wherein
a through-hole electrode penetrates at least one of the first semiconductor chip or the second semiconductor chip from a front surface to a back surface thereof, and
the through-hole electrode is electrically connected to the first bump and the second bump.

5. The semiconductor device of claim 1 , wherein the first bump is made of either a metal selected from the group consisting of copper, tin, nickel, silver, gold, cobalt, bismuth, zinc, indium, germanium, and tungsten, or a conductive metal compound containing a metal selected from the group consisting of copper, tin, nickel, silver, gold, cobalt, bismuth, zinc, indium, germanium, and tungsten.

6. The semiconductor device of claim 1 , wherein the second bump is made of either a metal selected from the group consisting of copper, tin, nickel, silver, gold, cobalt, bismuth, zinc, indium, germanium, and tungsten, or a conductive metal compound containing a metal selected from the group consisting of copper, tin, nickel, silver, gold, cobalt, bismuth, zinc, indium, germanium, and tungsten.

7. The semiconductor device of claim 1 , wherein the first electrode pad has a thickness of 0.3 μm to 5 μm.

8. The semiconductor device of claim 1 , wherein the first bump has a height of 4 μm to 60 μm.

9. The semiconductor device of claim 1 , wherein the second bump has a height of 2 μm to 50 μm.

10. The semiconductor device of claim 1 , wherein the recessed portion of the first bump has an upper surface which directly contacts the second bump.

11. The semiconductor device of claim 1 , wherein the recessed portion of the upper surface of the first bump is formed prior to contacting the second bump.

12. The semiconductor device of claim 2 , wherein the second bump has a diameter equal to or smaller than an inner diameter of the hollow cylindrical shape of the first electrode pad.

13. The semiconductor device of claim 2 , further comprising:
a first passivation layer that covers the first semiconductor chip, is sandwiched between the first bump and the first electrode pad, and has an opening in which the first electrode pad is exposed such that an end of the opening is located on the first electrode pad, wherein
the opening of the first passivation layer has a diameter smaller than a diameter of the first bump and larger than an inner diameter of the hollow cylindrical shape of the first electrode pad.

14. The semiconductor device of claim 2 , wherein the first bump has a diameter of 4 μm to 30 μm.

15. The semiconductor device of claim 2 , wherein the second bump has a diameter of 2 μm to 25 μm.

16. The semiconductor device of claim 2 , wherein the first electrode pad has an inner diameter of 2 μm to 25 μm.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Higuchi Yuichi

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title