Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-9978658-B2
Application number	US-201615361487-A
Country	US
Kind code	B2
Filing date	Nov 27, 2016
Priority date	Jun 8, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die;
an encapsulant material, wherein the first and second sidewalls of the die include vertical sidewall profile and the encapsulant material fully covers the first and second sidewalls of the die; and
wherein the encapsulant material comprises vertical portions and first and second lateral extended portions, wherein
the vertical portions fully cover the first and second sidewalls of the die,
the first lateral extended portions extend over peripheral portions of the first major surface of the die, and
the second lateral extended portions extend away from the die, wherein the second lateral extended portions include a top surface which is substantially coplanar with the second major surface of the die.

2. A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die, wherein each of the first and second sidewalls of the die includes a step profile;
a first encapsulant layer that covers the first major surface of the die; and
a second encapsulant layer that covers the first encapsulant layer and a portion of the first and second sidewalls of the die.

3. The semiconductor package of claim 2 wherein:
the first and second encapsulant layers are separate and distinct layers; and
the step profile of the first and second sidewalls of the die is defined by a first and a second sidewall portion, wherein the second sidewall portion is laterally extended relative to the first sidewall portion, and the first sidewall portion is adjacent to the first major surface of the die.

4. The semiconductor package of claim 3 wherein the second encapsulant layer covers the first sidewall portion without covering the second sidewall portion of the first and second sidewalls of the die.

5. The semiconductor package of claim 3 wherein the first encapsulant layer extends to cover the first sidewall portion, and the second encapsulant layer extends beyond the first encapsulant layer to cover the second sidewall portion of the first and second sidewalls of the die.

6. A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die, wherein each of the first and second sidewalls of the die includes a first and a second sidewall portion, and the second sidewall portion is laterally extended relative to the first sidewall portion to define a step profile of the first and second sidewalls; and
an encapsulant layer, wherein the encapsulant layer directly contacts and covers the first sidewall portion without covering the second sidewall portion of the first and second sidewalls of the die.

7. The semiconductor package of claim 6 wherein the encapsulant layer additionally overlaps the first major surface of the die.

8. The semiconductor package of claim 7 wherein the encapsulant layer directly contacts and covers the first major surface of the die.

9. The semiconductor package of claim 6 wherein the encapsulant layer is a first encapsulant layer and the semiconductor package additionally comprises a second encapsulant layer, wherein the second encapsulant layer is separate and distinct from the first encapsulant layer.

10. The semiconductor package of claim 9 wherein the first encapsulant layer additionally extends over and covers the first major surface of the die.

11. The semiconductor package of claim 10 wherein the second encapsulant layer is disposed over and covers the first encapsulant layer, wherein the second encapsulant layer extends beyond the first encapsulant layer to cover the second sidewall portion of the first and second sidewalls of the die.

12. The semiconductor package of claim 9 wherein the second encapsulant layer is disposed on and covers the first major surface of the die.

13. The semiconductor package of claim 12 wherein the first encapsulant layer extends over and covers the second encapsulant layer.

14. The semiconductor package of claim 6 wherein the encapsulant layer does not cover the first major surface of the die.

15. The semiconductor package of claim 6 wherein the second major surface of the die is exposed.

16. The semiconductor package of claim 15 wherein the encapsulant layer extends to cover the first major surface of the die.

17. The semiconductor package of claim 6 wherein the second sidewall portion of the first and second sidewalls of the die is devoid of encapsulant material.

18. The semiconductor package of claim 6 wherein the encapsulant layer does not contact the external electrical contacts of the die.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Dimaano Antonio Jr Bambalan
• Huang Rui
• Tan Hua Hong
• Le Kriangsak Sae
• Ho Beng Yeung
• De Vera Nelson Agbisit
• Robles Roel Adeva
• Micla Wedanni Linsangan

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W46/301

  for alignment · CPC title