Method of semiconductor fabrication with height control through active region profile

Patent metadata

Field	Value
Publication number	US-9978652-B2
Application number	US-201715612627-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Feb 13, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method includes forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices; extracting a profile of the regions; determining an etch recipe based on at least the profile of the regions; filling in the trenches with a dielectric material; and performing an etching process to the dielectric material using the etch recipe.

First claim

What is claimed is:

1. A method, comprising:
forming trenches on a semiconductor substrate, thereby defining regions for forming semiconductor devices;
extracting a profile of the regions;
determining an etch recipe based on at least the profile of the regions;
filling in the trenches with a dielectric material; and
performing an etching process to the dielectric material using the etch recipe.

2. The method of claim 1 , further comprising, before the forming of the trenches:
forming an etch mask over the semiconductor substrate, wherein the forming of the trenches includes etching the semiconductor substrate through openings of the etch mask.

3. The method of claim 2 , further comprising:
removing the etch mask before the extracting of the profile.

4. The method of claim 2 , further comprising:
removing the etch mask after the extracting of the profile.

5. The method of claim 1 , wherein the extracting of the profile includes measuring a sidewall angle of the regions.

6. The method of claim 5 , wherein the extracting of the profile further includes measuring a dimension of the trenches.

7. The method of claim 1 , wherein the extracting of the profile includes:
measuring sidewall angles at different locations of the regions; and
determining an average of the measured sidewall angles.

8. The method of claim 1 , wherein the etch recipe is determined based on the profile of the regions and a desired height of the regions after the performing of the etching process.

9. The method of claim 1 , further comprising, before the performing of the etching process:
performing a chemical mechanical polishing process or an etch-back process to the dielectric material.

10. The method of claim 1 , further comprising, after the performing of the etching process:
forming transistor source and drain features in the regions.

11. A method, comprising:
forming an etch mask on a substrate;
etching the substrate through openings of the etch mask, thereby forming trenches and ridges;
determining a profile of the ridges including the etch mask;
determining an etch recipe based on at least the profile;
filling the trenches with one or more dielectric materials; and
recessing the one or more dielectric materials using the etch recipe.

12. The method of claim 11 , wherein the filling of the trenches includes depositing the one or more dielectric materials on the etch mask.

13. The method of claim 12 , further comprising:
applying a chemical mechanical polishing (CMP) process to the one or more dielectric materials, wherein the etch mask serves as a polishing stop for the CMP process.

14. The method of claim 11 , wherein the etch mask remains over the ridges during the recessing of the one or more dielectric materials.

15. The method of claim 11 , further comprising removing the etch mask after the recessing of the one or more dielectric materials.

16. A method, comprising:
forming first ridge features on a substrate;
measuring a sidewall angle (SWA) of the first ridge features;
determining an etch dosage according to the SWA and a desired height of the first ridge features;
depositing a dielectric material over the substrate and covering the first ridge features; and
performing an etching process to the dielectric material with the etch dosage, thereby recessing the dielectric material and defining the first ridge features to have the desired height.

17. The method of claim 16 , further comprising measuring a dimension between two first ridge features, wherein the determining of the etch dosage also takes into account the dimension.

18. The method of claim 16 , wherein the determining of the etch dosage includes reading a lookup table that associates the etch dosage to the SWA.

19. The method of claim 16 , wherein the forming of the first ridge features includes:
forming an etch mask over the substrate; and
etching the substrate through openings of the etch mask with remaining portions of the substrate becoming the first ridge features.

20. The method of claim 19 , further comprising:
removing the etch mask before the measuring of the SWA.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chao Yi-Cheng
• Chang Che-Cheng
• Wu Po-Chi
• Li Jung-Jui

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title