Implant-free punch through doping layer formation for bulk FinFET structures

Patent metadata

Field	Value
Publication number	US-9514995-B1
Application number	US-201514718760-A
Country	US
Kind code	B1
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate having a top surface and first and second regions;
a plurality of parallel semiconductor fins extending from the top surface of the semiconductor substrate, one or more of the plurality of parallel semiconductor fins extending from the first region and one or more of the plurality of parallel semiconductor fins extending from the second region, the plurality of parallel semiconductor fins defining a plurality of channels;
a p-type punch through stop layer within the first region of the semiconductor substrate and the one or more parallel semiconductor fins extending from the first region, the p-type punch through stop layer including diffused p-type dopants;
an n-type punch through stop layer within the second region of the semiconductor substrate and the one or more parallel semiconductor fins extending from the second region, the n-type punch through stop layer including diffused n-type dopants;
a p-doped oxide layer partially filling the channels above the first region, the p-doped oxide layer directly contacting the top surface of the semiconductor substrate and the semiconductor fins extending from the first region;
an n-doped oxide layer partially filling the channels above the second region, the n-doped oxide layer directly contacting the top surface of the semiconductor substrate and the semiconductor fins extending from the second region; and
an undoped oxide layer partially filling the plurality of channels.

2. The semiconductor structure of claim 1 , wherein semiconductor substrate comprises a bulk silicon substrate.

3. The semiconductor structure of claim 1 , wherein the p-doped oxide layer consists essentially of borosilicate glass and the n-doped oxide layer consists essentially of phosphosilicate glass or arsenosilicate glass.

4. The structure of claim 3 , wherein the one or more parallel semiconductor fins extending from the first region are strained silicon fins and the one or more parallel semiconductor fins extending from the second region are strained silicon germanium fins.

5. The structure of claim 4 wherein the semiconductor substrate comprises a silicon germanium strain relaxed buffer layer.

6. The structure of claim 4 , wherein the p-doped oxide layer is thicker than the n-doped oxide layer.

7. The structure of claim 4 , wherein the p-type punch through stop layer and the n-type punch through stop layer extend substantially equal distances into the plurality of parallel semiconductor fins.

Assignees

• Globalfoundries Inc

Inventors

• Fogel Keith E
• Reznicek Alexander
• Sadana Devendra K
• Schepis Dominic J

Classifications

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title