Selective planishing method for making a semiconductor device

Patent metadata

Field	Value
Publication number	US-9972506-B2
Application number	US-201514684848-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	May 2, 2012
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

First claim

I claim:

1. A method for fabricating a plurality of semiconductor devices, the method comprising:
forming a leadframe from a flat sheet of base metal;
roughening a surface of the leadframe by plating the surface of the leadframe with at least one additional metal layer to create sites for attaching a semiconductor chip;
selectively planishing the surface of the leadframe to create flattened zones that are offset from the sites; and
attaching the semiconductor chip to each site.

2. The method of claim 1 wherein the sites are located on both sides of the leadframe.

3. The method of claim 2 further including selectively planishing flattened zones on both sides of the leadframe.

4. The method of claim 2 wherein the rough surface of the sites of the leadframe has an average roughness of 90±20 nm, enhancing the adhesion of the leadframe metal to a molding compound.

5. The method of claim 3 wherein the flattened zones created by the planishing have an average roughness of 35±20 nm, reducing the adhesion of the leadframe metal to a molding compound.

6. The method of claim 5 wherein the planishing process creating the flattened zones causes a thickness reduction of the rough surface of the leadframe by 10±5%.

7. The method of claim 1 wherein the flattened zones transition by a step into the rough surface of the leadframe.

8. The method of claim 7 wherein the step spacing the flattened zones from the rough surface of the leadframe equals the thickness reduction of the rough surface of the leadframe.

9. The method of claim 8 , further comprising cutting the sheet into strips.

10. The method of claim 1 wherein the rough surface of the leadframe is created by a flood roughening method.

11. The method of claim 1 wherein the rough surface of the leadframe is created by a mechanical roughening method.

12. A method, comprising:
roughening a first surface of a leadframe by plating the first surface of the leadframe with at least one additional metal layer to create a site for attaching a semiconductor chip;
selectively planishing the first surface of the leadframe to create a flattened zone that is offset from the site; and
attaching a semiconductor chip to the site.

13. The method of claim 12 further including roughening an opposite surface of a leadframe by plating the opposite surface of the leadframe with at least one additional metal layer to create another site for attaching another semiconductor chip.

14. The method of claim 13 further including selectively planishing another flattened zone on the opposite surface of the leadframe.

15. The method of claim 12 wherein the rough first surface of the site of the leadframe has an average roughness of 90±20 nm, enhancing the adhesion of the leadframe metal to a molding compound.

16. The method of claim 12 wherein the flattened zone created by the planishing has an average roughness of 35±20 nm, reducing the adhesion of the leadframe metal to a molding compound.

17. The method of claim 16 wherein the planishing process creating the flattened zone causes a thickness reduction of the rough first surface of the leadframe by 10±5%.

18. The method of claim 17 wherein the flattened zone transitions by a step into the rough first surface of the leadframe.

19. The method of claim 18 wherein the step spacing the flattened zone from the rough first surface of the leadframe equals the thickness reduction of the rough first surface of the leadframe.

20. The method of claim 12 wherein the rough first surface of the leadframe is created by a flood roughening method.

21. The method of claim 12 wherein the rough first surface of the leadframe is created by a mechanical roughening method.

Assignees

• Texas Instruments Inc

Inventors

• Abbott Donald C

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W70/438

  of side rails, e.g. having holes · CPC title