Thyristor random access memory device and method

Patent metadata

Field	Value
Publication number	US-9954075-B2
Application number	US-201615284017-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Jun 29, 2010
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

First claim

What is claimed is:

1. A method comprising:
forming two vertically coupled P-N junctions on a first substrate;
forming a conductor region over the two vertically coupled P-N junctions;
flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate;
forming a third vertically coupled P-N junction on a back side of a portion of the first substrate;
forming a control line between two of the vertically coupled P-N junctions;
forming a buried transmission line from a portion of the conductor region; and
forming a second transmission line on top of the third vertically coupled P-N junction.

2. The method of claim 1 , wherein forming two vertically coupled P-N junctions on a first substrate includes forming on a P-doped silicon substrate.

3. The method of claim 1 , wherein forming a conductor region over the two vertically coupled P-N junctions includes forming a titanium conductor region.

4. The method of claim 1 , wherein forming a conductor region over the two vertically coupled P-N junctions includes forming a tungsten conductor region.

5. The method of claim 1 , further including forming an amorphous silicon material over the conductor region prior to flipping the first substrate, and bonding the conductor region to the dielectric material of the second substrate.

6. A method comprising:
forming a vertical stack of alternating conductivity type semiconductor material, including:
forming two vertically coupled P-N junctions on a first substrate;
forming a conductor region over the two vertically coupled P-N junctions;
flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate;
forming a third vertically coupled P-N junction on a back side of a portion of the first substrate;

forming trenches in the vertical stack to form an array of vertical pillars of alternating conductivity type semiconductor material; and
forming at least one control line in a trench between two adjacent pillars separated from a channel region by a dielectric material.

7. The method of claim 6 , wherein forming at least one control line in the trench includes forming a single control line to operate a pair of adjacent channel regions on adjacent pillars in the array at the same time.

8. The method of claim 6 , wherein forming at least one control line in the trench includes forming a pair of split control lines in the same trench to operate adjacent channel regions on adjacent pillars in the array separately.

9. The method of claim 6 , wherein forming trenches includes forming trenches down to the conductor region.

10. The method of claim 6 , further including etching a portion of the vertical stack underneath the at least one control line.

11. The method of claim 6 , wherein forming two vertically coupled P-N junctions on a first substrate includes forming two vertically coupled P-N junctions on a P-type silicon substrate.

12. The method of claim 6 , wherein bonding the conductor region to the dielectric material of the second substrate includes bonding the conductor region to a silicon oxide material on a silicon substrate.

13. The method of claim 6 , further including forming a buried transmission line from a portion of the conductor region.

14. The method of claim 13 , further including forming a second transmission line on top of the vertical pillars.

15. A method comprising:
forming a P-N-P layer structure to form a first substrate;
forming a conductor region over the first substrate;
flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate;
forming an N layer on a back side of a portion of the first substrate;
forming a trench at least partially through the N layer and the P-N-P layer; and
forming a control line within the trench.

16. The method of claim 15 , further including forming a buried transmission line from a portion of the conductor region.

17. The method of claim 15 , further including forming a second transmission line on top of the N layer.

18. The method of claim 15 , wherein bonding the conductor region includes bonding using amorphous silicon.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Zahurak John K
• Violette Michael P

Classifications

• H10D84/60

  characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs (H10D84/40 takes precedence) · CPC title

• H10B99/20 Primary

  comprising memory cells having thyristors · CPC title

• H01L29/66363 Primary

  Electricity · mapped topic

• H01L29/42308

  Electricity · mapped topic

• H01L29/74

  Electricity · mapped topic