Memory cell with reduced parasitic capacitance and method of manufacturing the same
US-2024334680-A1 · Oct 3, 2024 · US
US8999837B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8999837-B2 |
| Application number | US-201314137339-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 20, 2013 |
| Priority date | Aug 26, 2013 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a semiconductor device, comprising, the method comprising: forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, recessed first conductive patterns in the openings; removing the sacrificial spacers to define air gaps; forming a liner layer to cap the first conductive patterns and the air gaps; forming second conduct…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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