Transistor with improved air spacer

Patent metadata

Field	Value
Publication number	US-9941352-B1
Application number	US-201615285728-A
Country	US
Kind code	B1
Filing date	Oct 5, 2016
Priority date	Oct 5, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, the method comprising:
forming a gate contact in contact with a gate stack;
after forming the gate contact, removing a spacer surrounding at least a portion of the gate stack, wherein the removing forms a trench surrounding the gate stack and stopping at the gate contact; and
depositing an insulating material within the trench to form an air gap spacer within the trench comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack.

2. The method of claim 1 , wherein forming the gate contact comprises:
forming the gate contact in contact with a portion of a top surface of a gate of the gate stack, and wrapping the gate contact around a portion of the gate and a portion of an underlying dielectric layer of the gate stack.

3. The method of claim 1 , wherein forming the gate contact comprises:
removing a portion of the spacer in contact with an end portion of the gate stack, wherein the removing exposes an end portion of a gate of the gate stack and an underlying dielectric layer, and further exposes sidewalls of the gate and underlying dielectric layer.

4. The method of claim 3 , wherein forming the gate contact further comprises:
removing a portion of a cap layer formed on the gate, the etching exposing a top surface of a gate at the end portion of the gate stack;
removing a portion of an insulating layer adjacent to the gate stack; and
forming the gate contact in contact with at least the top surface of the gate, the exposed sidewalls of the gate, and the exposed sidewalls of the underlying dielectric layer.

5. The method of claim 1 , further comprising:
prior to forming the gate contact,
forming a source contact in contact with a portion of a source region of a substrate and a sidewall of the spacer; and
forming a drain contact in contact with a portion of a drain region of the substrate and a sidewall of the spacer.

6. The method of claim 5 , wherein forming the source contact and the drain contact comprises:
depositing a dielectric material in contact with the source region, drain region, and spacer;
forming a first contact trench adjacent to the spacer, the first contact trench exposing the portion of the source region;
forming a second contact trench adjacent to the spacer, the second contact trench exposing the portion of the drain region; and
filling the first contact trench and the second contact trench with a contact material;
removing a portion of the first spacer at one end of the gate stack.

7. The method of claim 1 , wherein forming the air gap spacer comprises:
non-conformally depositing the insulating material within the trench, wherein the non-conformal deposition deposits a greater amount of the insulating material at a top portion of the trench than at a bottom portion of the trench, and wherein the non-conformal deposition forms an air gap between a top portion of the air gap spacer and a bottom portion of the air gap spacer.

8. The method of claim 1 , further comprising forming the gate stack, wherein forming the gate stack comprises:
forming a replacement gate structure on a substrate; and
forming the spacer in contact with the replacement gate structure.

9. The method of claim 8 , further comprising:
after forming the spacer, forming a source region and a drain region within the substrate.

10. The method of claim 8 , further comprising:
after the spacer has been formed, selectively removing the replacement gate stack, wherein the selective removal exposes an active area within the substrate and sidewalls of the spacer;
forming a dielectric layer on and in contact with the active area; and
forming a conductive gate on and in contact with the dielectric layer.

11. A method for fabricating a semiconductor structure, the method comprising:
forming a plurality of gate contacts, wherein each gate contact of the plurality of gate contacts is in contact with a gate stack of a plurality of gate stacks;
after forming the plurality of gate contacts and for each gate stack of the plurality of gate stacks, removing a spacer surrounding at least a portion of the gate stack, wherein the removing forms a trench surrounding the gate stack and stopping at the gate contact; and
depositing, for each gate stack of the plurality of gate stacks, an insulating material within the trench to form an air gap spacer within each trench comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack.

12. The method of claim 11 , wherein forming each gate contact of the plurality of gate contact comprises:
forming the gate contact in contact with a portion of a top surface of a gate of the gate stack, and wrapping the gate contact around a portion of the gate and a portion of an underlying dielectric layer of the gate stack.

13. The method of claim 11 , wherein forming each gate contact of the plurality of gate contact comprises:
removing a portion of the spacer in contact with an end portion of the gate stack, wherein the removing exposes an end portion of a gate of the gate stack and an underlying dielectric layer, and further exposes sidewalls of the gate and underlying dielectric layer.

14. The method of claim 13 , wherein forming each gate contact of the plurality of gate contact further comprises:
removing a portion of a cap layer formed on the gate, the etching exposing a top surface of a gate at the end portion of the gate stack;
removing a portion of an insulating layer adjacent to the gate stack; and
forming the gate contact in contact with at least the top surface of the gate, the exposed sidewalls of the gate, and the exposed sidewalls of the underlying dielectric layer.

15. The method of claim 11 , further comprising:
prior to forming each gate contact of the plurality of gate contacts,
forming a plurality of source contacts, wherein each source contact is in contact with a portion of a source region of a substrate and a sidewall of one of the spacers; and
forming a plurality drain contacts, wherein each drain contact in contact with a portion of a drain region of the substrate and a sidewall of one of the spacers.

16. The method of claim 15 , wherein forming each source contact of the plurality of source contacts and each drain contact of the plurality of drain contacts comprises:
depositing a dielectric material in contact with the source region, drain region, and spacer;
forming a first contact trench adjacent to the spacer, the first contact trench exposing the portion of the source region;
forming a second contact trench adjacent to the spacer, the second contact trench exposing the portion of the drain region; and
filling the first contact trench and the second contact trench with a contact material;
removing a portion of the first spacer at one end of the gate stack.

17. The method of claim 11 , wherein forming the air gap spacer comprises:
non-conformally depositing the insulating material within the trench, wherein the non-conformal deposition deposits a greater amount of the insulating material at a top portion of the trench than at a bottom portion of the trench, and wherein the non-conformal deposition forms an air gap between a top portion of the air gap spacer and a bottom portion of the air gap spacer.

18. The method of claim 11 , further comprising forming the plurality of gate stacks, wherein forming each gate stack in the plurality of gate stacks comprises:
forming a replacem

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title