Semiconductor device with air gap

Patent metadata

Field	Value
Publication number	US-9245849-B2
Application number	US-201514632781-A
Country	US
Kind code	B2
Filing date	Feb 26, 2015
Priority date	Aug 26, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.

First claim

What is claimed is:

1. A semiconductor device, including isolation structures having openings exposing surface portions of a substrate, and conductive structures formed in the openings, the conductive structures comprising:
recessed first conductive patterns formed in the openings;
air gaps defined between sidewalls of the openings and the recessed first conductive patterns;
capping patterns to cap the air gaps;
second conductive patterns formed over top surfaces of the first conductive patterns and the capping patterns and on upper sidewalls of the openings, the second conductive patterns including a metal silicide; and
third conductive patterns formed over the second conductive patterns.

2. The semiconductor device according to claim 1 , wherein the conductive structures comprise plugs.

3. The semiconductor device according to claim 1 , wherein the metal silicide comprises a silicide of a polysilicon layer.

4. The semiconductor device according to claim 1 , wherein the first conductive patterns comprise a polysilicon layer, and the third conductive patterns comprise a metal layer.

5. The semiconductor device according to claim 1 , wherein the isolation structures comprise a silicon nitride.

6. A semiconductor device comprising:
a plurality of conductive structures formed over a substrate, the plurality of conductive structures including conductive patterns;
protective spacers formed on sidewalls of the plurality of conductive structures;
isolation structures formed between the plurality of conductive structures, the isolation structures including a plurality of openings;
recessed first conductive patterns formed in the openings;
air gaps defined between the conductive patterns and the recessed first conductive patterns;
capping patterns to cap the air gaps;
second conductive patterns formed over top surfaces of the first conductive patterns, the capping patterns, and on upper sidewalls of the openings, the second conductive patterns including a metal silicide; and
third conductive patterns formed over the second conductive patterns.

7. The semiconductor device according to claim 6 , wherein the metal silicide comprises a silicide of a polysilicon layer.

8. The semiconductor device according to claim 6 , wherein the first conductive patterns comprise a polysilicon layer, and the third conductive patterns comprise a metal layer.

9. The semiconductor device according to claim 6 , wherein the isolation structures and the protective spacers comprise a silicon nitride.

10. The semiconductor device according to claim 6 , wherein stack structures of the first conductive patterns, the second conductive patterns and the third conductive patterns become plugs.

11. The semiconductor device according to claim 6 , further comprising:
gate type transistors buried in the substrate,
wherein the first conductive patterns are to be connected to source regions or drain regions of the gate type transistors.

12. A memory device comprising:
a substrate;
gate type transistors buried in the substrate;
a plurality of bit line structures, formed over the substrate, to be connected to the buried gate type transistors;
isolation structures including a plurality of openings defined between the plurality of bit line structures;
silicon plugs formed in the openings;
air gaps defined between the silicon plugs and the plurality of bit line structures;
capping patterns to cap the air gaps;
an ohmic contact layer covering the silicon plugs, the capping patterns, and sidewalls of the plurality of bit line structures, the ohmic contact layer including a metal silicide;
metal plugs formed over the ohmic contact layer; and
memory elements formed over the metal plugs.

13. The memory device according to claim 12 , wherein the metal silicide comprises a silicide of a polysilicon layer.

14. The memory device according to claim 12 , further comprising:
protective spacers formed on the sidewalls of the plurality of bit line structures; and
spacers surrounding sidewalls of the silicon plugs,
wherein the air gaps are defined between the protective spacers and the spacers.

15. The memory device according to claim 14 , wherein the protective spacers and the spacers comprise a silicon nitride.

16. The memory device according to claim 12 , wherein bottom portions of the openings are enlarged sideward.

17. The memory device according to claim 12 , further comprising:
a dielectric layer formed between the plurality of bit line structures and the substrate, the dielectric layer including contact holes to expose a surface of the substrate;
bit line contact plugs formed in the contact holes, the bit line contact plugs having a width smaller than a diameter of the contact holes; and
contact spacers formed around the bit line contact plugs.

18. The memory device according to claim 17 , wherein the bit line structures and the bit line contact plugs have a same width.

19. The memory device according to claim 14 , wherein the spacers extend to cover the sidewalls of the plurality of bit line structures.

20. The memory device according to claim 12 , further comprising:
planar gate type transistors formed in a non-memory cell region of the substrate.

Assignees

• Sk Hynix Inc

Inventors

• Park Jong-Kook
• Song Han-Sang
• Lee Jin-Yul
• Lee Chang-Ki

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title