Semiconductor device including air gaps and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9293362-B2
Application number	US-201313801033-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Dec 26, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a plurality of bit line structures over a substrate;
forming contact holes between the bit line structures;
forming sacrificial spacers over sidewalls of the contact holes;
forming first plugs recessed into the respective contact holes;
forming air gaps by removing the sacrificial spacers;
forming capping structures entirely capping the air gaps while exposing top surfaces of the first plugs; and
forming second plugs over the first plugs,
wherein the capping structures are formed after the air gaps are formed,
wherein the forming of capping structures comprises:
forming capping layers over the top surfaces and sidewalls of the first plugs;
forming a passivation layer over the entire surface in which the capping layers are formed; and
selectively removing the capping layers and the passivation layer to form the capping structures having capping layer patterns and passivation layer patterns while exposing the top surfaces of the first plugs.

2. The method of claim 1 , wherein the selectively removing of the capping layers and the passivation layer comprises:
selectively etching the passivation layer using the capping layers as an etch barrier to Rain the passivation layer patterns having a spacer type; and
selectively etching the capping layers to form the capping layer patterns to expose the top surfaces of the first plugs.

3. The method of claim 1 , wherein the forming of capping layers over the top surfaces and sidewalls of the first plugs comprises:
performing a plasma oxidization process on the top surfaces of the first plugs.

4. The method of claim 1 , wherein the first plugs comprise a silicon-containing layer.

5. The method of claim 1 , wherein the second plugs comprise a metal-containing layer.

6. The method of claim 1 , further comprising:
forming spacers over the sidewalls of the bit line structures before the forming the contact holes.

7. The method of claim 1 , wherein each of the capping structures comprises a capping layer and a passivation layer stacked over the capping layer.

8. A method of fabricating a semiconductor device, comprising:
forming a plurality of bit line structures over a substrate;
forming contact holes between the bit line structures;
forming sacrificial spacers on sidewalls of the contact holes;
forming silicon plugs recessed into the respective contact holes;
forming air gaps by removing the sacrificial spacers;
forming capping structures entirely capping the air gaps while exposing top surfaces of the silicon plugs;
forming ohmic contact layers over the silicon plugs; and
forming metal plugs over the ohmic contact layers,
wherein the capping structures are formed after the air gaps are formed,
wherein:
each silicon plug comprises a polysilicon layer, and
each capping layer pattern comprises silicon oxide generated by oxidizing a silicon plug corresponding thereto.

9. The method of claim 8 , wherein the forming of capping structures comprises:
performing a plasma oxidation process on the top surfaces of the silicon plugs;
forming silicon nitride over an entire surface including the oxide; and
selectively removing the oxide and the silicon nitride so that the top surfaces of the silicon plugs are exposed.

10. The method of claim 8 , wherein the ohmic contact layers comprise cobalt silicide.

11. The method of claim 8 , wherein the metal plugs comprise tungsten.

12. The method of claim 8 , wherein the sacrificial spacers comprise titanium nitride.

13. The method of claim 8 , further comprising:
forming spacers on the sidewalls of the bit line structures before the forming the contact holes.

14. The method of claim 8 , wherein each of the capping structures comprises a capping layer and a passivation layer stacked over the capping layer.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam-Yeal
• Yeom Seung-Jin
• Lim Sung-Won
• Hong Seung-Hee
• Lee Hyo-Seok
• Kim Dong-Seok
• Kim Seung-Bum
• Kim Sei-Jin

Classifications

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title