Method for processing a semiconductor layer, method for processing a silicon substrate, and method for processing a silicon layer

US9941111B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9941111-B2
Application numberUS-201514724947-A
CountryUS
Kind codeB2
Filing dateMay 29, 2015
Priority dateMay 29, 2015
Publication dateApr 10, 2018
Grant dateApr 10, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing a semiconductor substrate, the semiconductor substrate comprising a semiconductor layer and a native oxide layer disposed on at least one surface of the semiconductor layer, wherein the semiconductor layer is a silicon or a silicon carbide layer, the method comprising: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; removing the native oxide layer from the semiconductor substrate comprising etching the native oxide layer and etching from between 1 and 100 atomic layers of the semiconductor layer below the native oxide layer by introducing the etch plasma into the processing chamber; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer, wherein the dielectric layer is deposited by chemical vapor deposition using a hydrocarbon containing precursor, and wherein an interface between the semiconductor layer and the dielectric layer has an interface state density of less than about 2× 10 13 cm −2 eV −1 ; wherein the etch plasma is generated in the plasma chamber of the remote plasma source from a halogen containing gas. 2. The method according to claim 1 , wherein the dielectric layer is deposited by plasma-enhanced chemical vapor deposition. 3. The method according to claim 1 , wherein the dielectric layer comprises at least one of a carbon based dielectric material or a silicon based dielectric material. 4. The method according to claim 1 , wherein the semiconductor layer comprises silicon and the halogen containing gas comprises fluorine. 5. A method for processing a silicon substrate, the silicon substrate having a native oxide layer disposed on at least one surface of the silicon substrate, the method comprising: bringing the silicon substrate into a processing region of a processing chamber; providing a vacuum in the processing region; pretreating the at least one surface of the silicon substrate using an etch plasma that is provided in the processing region by a remote plasma source coupled to the processing chamber, wherein the etch plasma is generated from a fluorine containing gas; and, subsequently, wherein pretreating the silicon substrate further comprises etching so as to remove the native oxide layer and to remove an amount of the silicon layer the at least one surface less than or equal to 100 nm; forming a gate dielectric layer, wherein forming the gate dielectric layer comprises depositing a dielectric layer directly on the at least one surface of the silicon substrate by vapor deposition, wherein the vapor deposition is carried out in the processing region, wherein depositing the dielectric layer comprises introducing a hydrogen containing gas into the processing region during depositing the dielectric layer; and taking the silicon substrate out of the processing chamber, wherein the deposited dielectric layer comprises hydrogenated amorphous carbon. 6. The method according to claim 5 , wherein pretreating the at least one surface of the silicon substrate comprises completely removing native oxide from the at least one surface of the silicon substrate. 7. The method according to claim 5 , wherein pretreating the at least one surface of the silicon substrate and depositing the dielectric layer are carried out under vacuum conditions so that the at least one surface of the silicon substrate remains free of native oxide after pretreating and before depositing the dielectric layer. 8. The method according to claim 5 , wherein the fluorine containing gas is diluted with an inert gas to a gas mixture containing more than 99 molar percentage of the inert gas. 9. The method according to claim 5 , wherein depositing the dielectric layer comprises depositing amorphous carbon. 10. The method according to claim 5 , wherein depositing the dielectric layer comprises depositing silicon oxide. 11. The method according to claim 5 , wherein depositing the dielectric layer comprises depositing diamond-like carbon. 12. The method according to claim 5 , wherein depositing the dielectric layer comprises depositing silicon doped hydrogenated amorphous carbon.

Assignees

Inventors

Classifications

  • by dry cleaning only (H10P70/52 takes precedence) · CPC title

  • of Group IV materials · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • by exposure to a plasma · CPC title

  • In-situ cleaning · CPC title

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What does patent US9941111B2 cover?
According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P14/6902. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).