Integrated oxide recess and floating gate fin trimming

Patent metadata

Field	Value
Publication number	US-9378978-B2
Application number	US-201414448901-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Jul 31, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

First claim

The invention claimed is:

1. A method of forming a floating gate, the method comprising:
transferring a patterned substrate into a substrate processing mainframe, wherein the patterned substrate comprises two polysilicon floating gates separated by shallow trench isolation silicon oxide gapfill dielectric, wherein the two polysilicon floating gates each have vertical sidewalls;
transferring the patterned substrate into a first substrate processing chamber mounted on the substrate processing mainframe;
flowing a fluorine-containing precursor and a hydrogen-containing precursor into a first remote plasma region within the first substrate processing chamber while striking a plasma to form first plasma effluents from a combination of the fluorine-containing precursor and the hydrogen-containing precursor;
flowing the first plasma effluents into a first substrate processing region within the first substrate processing chamber; wherein the first substrate processing region houses the patterned substrate;
reacting the first plasma effluents with the shallow trench isolation silicon oxide gapfill dielectric to form solid residue and sublimating the solid residue;
transferring the patterned substrate from the first substrate processing chamber to a second substrate processing chamber mounted on the substrate processing mainframe;
flowing a fluorine-containing precursor into a second remote plasma region within the second substrate processing chamber while striking a plasma to form second plasma effluents and flowing the second plasma effluents through a showerhead into a second substrate processing region housing the patterned substrate within the second substrate processing chamber;
isotropically etching the two polysilicon floating gates to thin their width and form sidewalls which are again vertical by reacting the second plasma effluents with the two polysilicon floating gates; and
removing the patterned substrate from the substrate processing mainframe, wherein the patterned substrate is not exposed to atmosphere between transferring the patterned substrate into the substrate processing mainframe and removing the patterned substrate from the substrate processing mainframe.

2. The method of claim 1 , wherein sublimating the solid residue comprises raising a temperature of the patterned substrate.

3. The method of claim 1 , further comprising depositing a conformal inter-poly dielectric layer after isotropically etching the two polysilicon floating gates.

4. The method of claim 1 , wherein a sequence of forming the solid residue and sublimating the solid residue occurs at least two times.

5. The method of claim 1 , wherein the fluorine-containing precursor is nitrogen trifluoride.

6. The method of claim 1 , wherein the hydrogen-containing precursor comprises at least one of hydrogen (H 2 ) and ammonia.

7. The method of claim 1 , wherein each sidewall of the two polysilicon floating gates is within 2° of vertical.

8. The method of claim 1 , wherein an electron temperature in the second substrate processing region during reacting the second plasma effluents is below 0.5 eV.

9. A method of forming a floating gate, the method comprising:
transferring a patterned substrate into a substrate processing mainframe, wherein the patterned substrate comprises two polysilicon floating gates separated by shallow trench isolation silicon oxide gapfill dielectric, wherein the two polysilicon floating gates each have vertical sidewalls;
transferring the patterned substrate into a first substrate processing chamber mounted on the substrate processing mainframe;
flowing a fluorine-containing precursor into a first remote plasma region within the first substrate processing chamber while striking a plasma to form first plasma effluents;
flowing the plasma effluents into a first substrate processing region within the first substrate processing chamber; wherein the first substrate processing region houses the patterned substrate; and flowing an unexcited precursor directly into the first substrate processing region without first passing the unexcited precursor through any plasma prior to entering the first substrate processing region;
reacting the plasma effluents with the shallow trench isolation silicon oxide gapfill dielectric;
transferring the patterned substrate from the first substrate processing chamber to a second substrate processing chamber mounted on the substrate processing mainframe;
flowing a fluorine-containing precursor into a second remote plasma region within the second substrate processing chamber while striking a plasma to form second plasma effluents and flowing the second plasma effluents through a showerhead into a second substrate processing region housing the patterned substrate within the second substrate processing chamber;
isotropically etching the two polysilicon floating gates to reduce from an initial floating gate width to a final floating gate width and form sidewalls which are again essentially vertical by reacting the second plasma effluents with the two polysilicon floating gates; and
removing the patterned substrate from the substrate processing mainframe, wherein the patterned substrate is not exposed to atmosphere between transferring the patterned substrate into the substrate processing mainframe and removing the patterned substrate from the substrate processing mainframe.

10. The method of claim 9 , wherein the unexcited precursor comprises water or an alcohol.

11. The method of claim 9 , wherein the unexcited precursor comprises NxHy where x and y are greater than or equal to one.

12. The method of claim 9 , wherein the second remote plasma region is devoid of oxygen during flowing the fluorine-containing precursor into the second remote plasma region.

13. The method of claim 9 , wherein the second remote plasma region is devoid of hydrogen during flowing the fluorine-containing precursor into the second remote plasma region.

14. The method of claim 9 , wherein an electron temperature in the first substrate processing region during reacting the first plasma effluents and in the second substrate processing region during reacting the second plasma effluents are each below 0.5 eV.

15. The method of claim 9 , wherein the final floating gate width is less than 80% of the initial floating gate width.

Assignees

• Applied Materials Inc

Inventors

• Purayath Vinod R
• Thakur Randhir
• Venkataraman Shankar
• Ingle Nitin K

Classifications

• H10P72/33

  into and out of processing chamber · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title